Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
73.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	31	53	63.10

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	28	20	41.67	100	1	1	0
cr_modeXdummyXnum_lanes	36	3	33	91.67	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1165	1			T2	2		T4	2		T5	4
auto[SpiFlashAddrCfg]	884	1			T2	2		T4	18		T6	2
auto[SpiFlashAddr3b]	1002	1			T2	8		T7	4		T10	4
auto[SpiFlashAddr4b]	873	1			T2	2		T6	12		T99	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3022

1

T2

14

T4

20

T5

4

auto[1]

902

1

T70

24

T74

6

T71

16

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2037

1

T2

6

T4

18

T5

4

auto[1]

1887

1

T2

8

T4

2

T6

12

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1605	1			T2	4		T4	2		T5	4
values[1]	84	1			T70	2		T26	2		T195	2
values[2]	150	1			T42	6		T82	2		T100	6
values[3]	194	1			T101	2		T42	6		T82	2
values[4]	183	1			T6	4		T99	1		T101	4
values[5]	156	1			T4	2		T42	6		T169	6
values[6]	179	1			T99	6		T100	4		T124	2
values[7]	180	1			T4	2		T7	2		T10	4
values[8]	1193	1			T2	10		T4	14		T6	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3304

1

T2

14

T4

20

T5

4

auto[1]

620

1

T10

7

T99

7

T100

26

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3804

1

T2

14

T4

20

T5

4

write

120

1

T71

4

T72

2

T73

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1844

1

T2

8

T4

10

T5

4

valids[0x1]

2080

1

T2

6

T4

10

T6

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	224	1			T2	2		T6	6		T9	2
internal_process_ops[0x5a]	128	1			T107	2		T108	2		T224	2
internal_process_ops[0x05]	226	1			T6	4		T7	2		T8	8
internal_process_ops[0x35]	188	1			T70	4		T122	12		T107	6
internal_process_ops[0x15]	188	1			T4	2		T8	6		T122	6
internal_process_ops[0x03]	324	1			T2	2		T6	4		T7	2
internal_process_ops[0x0b]	256	1			T2	2		T4	6		T6	2
internal_process_ops[0x3b]	318	1			T10	3		T70	2		T100	6
internal_process_ops[0x6b]	266	1			T2	6		T4	2		T99	1
internal_process_ops[0xbb]	303	1			T4	4		T7	2		T10	4
internal_process_ops[0xeb]	274	1			T70	2		T124	2		T198	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3870

1

T2

14

T4

20

T5

4

auto[1]

54

1

T71

4

T72

2

T73

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3924

1

T2

14

T4

20

T5

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	28	20	41.67	28
Automatically Generated Cross Bins	48	28	20	41.67	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[write]	*	*	*	--	--	16

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

870

1

T2

2

T4

2

T5

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

262

1

T70

6

T74

2

T71

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

505

1

T2

2

T4

18

T6

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

148

1

T70

6

T74

4

T71

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

525

1

T2

8

T7

4

T101

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

248

1

T70

2

T72

8

T91

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

436

1

T2

2

T6

12

T122

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

190

1

T70

10

T71

2

T72

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

16

1

T305

12

T306

4

-

-

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

6

1

T71

4

T72

2

-

-

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

16

1

T242

6

T223

2

T307

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

8

1

T83

2

T86

2

T304

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

18

1

T261

2

T278

4

T300

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

30

1

T80

8

T83

2

T85

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

16

1

T242

4

T223

2

T220

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

10

1

T73

6

T81

2

T84

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11

1

T308

5

T309

6

-

-

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

207

1

T10

3

T100

10

T124

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

181

1

T10

4

T99

1

T100

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

221

1

T99

6

T100

10

T124

14

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	3	33	91.67	3

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0] , values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	310	1			T5	4		T6	2		T23	2
auto[0]	values[0]	valids[0x1]	1227	1			T2	4		T4	2		T6	14
auto[0]	values[1]	valids[0x1]	74	1			T70	2		T26	2		T195	2
auto[0]	values[2]	valids[0x0]	96	1			T42	6		T74	2		T215	4
auto[0]	values[2]	valids[0x1]	23	1			T82	2		T205	4		T91	2
auto[0]	values[3]	valids[0x0]	94	1			T101	2		T42	4		T82	2
auto[0]	values[3]	valids[0x1]	51	1			T42	2		T194	2		T196	2
auto[0]	values[4]	valids[0x0]	78	1			T6	4		T272	2		T244	6
auto[0]	values[4]	valids[0x1]	61	1			T101	4		T123	2		T107	2
auto[0]	values[5]	valids[0x0]	62	1			T4	2		T42	6		T195	2
auto[0]	values[5]	valids[0x1]	52	1			T205	2		T272	8		T244	2
auto[0]	values[6]	valids[0x0]	80	1			T198	4		T103	2		T77	4
auto[0]	values[6]	valids[0x1]	60	1			T205	2		T193	2		T229	4
auto[0]	values[7]	valids[0x0]	66	1			T26	2		T243	2		T230	6
auto[0]	values[7]	valids[0x1]	43	1			T4	2		T7	2		T70	2
auto[0]	values[8]	valids[0x0]	629	1			T2	8		T4	8		T6	2
auto[0]	values[8]	valids[0x1]	298	1			T2	2		T4	6		T6	4
auto[1]	values[0]	valids[0x1]	68	1			T124	7		T310	7		T89	5
auto[1]	values[1]	valids[0x1]	10	1			T308	5		T311	3		T312	2
auto[1]	values[2]	valids[0x0]	29	1			T100	6		T169	6		T313	7
auto[1]	values[2]	valids[0x1]	2	1			T312	2		-	-		-	-
auto[1]	values[3]	valids[0x0]	45	1			T124	6		T89	4		T314	3
auto[1]	values[3]	valids[0x1]	4	1			T315	1		T316	3		-	-
auto[1]	values[4]	valids[0x0]	34	1			T99	1		T100	5		T317	4
auto[1]	values[4]	valids[0x1]	10	1			T124	2		T318	2		T319	2
auto[1]	values[5]	valids[0x0]	33	1			T320	5		T310	5		T314	4
auto[1]	values[5]	valids[0x1]	9	1			T169	6		T321	3		-	-
auto[1]	values[6]	valids[0x0]	18	1			T99	6		T124	2		T320	3
auto[1]	values[6]	valids[0x1]	21	1			T100	4		T322	5		T323	6
auto[1]	values[7]	valids[0x0]	51	1			T10	4		T169	3		T320	5
auto[1]	values[7]	valids[0x1]	20	1			T100	6		T324	4		T309	6
auto[1]	values[8]	valids[0x0]	219	1			T10	3		T100	5		T124	5
auto[1]	values[8]	valids[0x1]	47	1			T169	2		T313	9		T325	4