Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1523858 1 T2 1 T4 1 T5 4288


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1414244 1 T2 1 T4 1 T5 4288
auto[1] 109614 1 T7 256 T8 16166 T42 3548


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 322598 1 T2 1 T4 1 T5 1751
auto[524288:1048575] 141147 1 T7 1575 T8 2559 T10 96
auto[1048576:1572863] 184735 1 T5 13 T8 13179 T10 1382
auto[1572864:2097151] 152872 1 T10 371 T99 357 T122 6635
auto[2097152:2621439] 159653 1 T5 845 T8 1220 T10 891
auto[2621440:3145727] 156263 1 T5 775 T7 2 T8 1448
auto[3145728:3670015] 178077 1 T5 13 T7 525 T8 13881
auto[3670016:4194303] 228513 1 T5 891 T7 1 T8 4289


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 123787 1 T2 1 T4 1 T5 101
auto[1] 1400071 1 T5 4187 T7 2169 T8 30446


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1523858 1 T2 1 T4 1 T5 4288


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 244323 1 T2 1 T4 1 T5 1751
auto[0] auto[0] auto[0:524287] auto[1] 78275 1 T7 131 T8 8330 T42 3548
auto[0] auto[0] auto[524288:1048575] auto[0] 137248 1 T7 1575 T8 14 T10 96
auto[0] auto[0] auto[524288:1048575] auto[1] 3899 1 T8 2545 T108 482 T189 5
auto[0] auto[0] auto[1048576:1572863] auto[0] 178966 1 T5 13 T8 10510 T10 1382
auto[0] auto[0] auto[1048576:1572863] auto[1] 5769 1 T8 2669 T190 1 T98 288
auto[0] auto[0] auto[1572864:2097151] auto[0] 151888 1 T10 371 T99 357 T122 6635
auto[0] auto[0] auto[1572864:2097151] auto[1] 984 1 T190 256 T191 254 T192 339
auto[0] auto[0] auto[2097152:2621439] auto[0] 158936 1 T5 845 T8 1089 T10 891
auto[0] auto[0] auto[2097152:2621439] auto[1] 717 1 T8 131 T108 5 T94 1
auto[0] auto[0] auto[2621440:3145727] auto[0] 147743 1 T5 775 T7 2 T8 1447
auto[0] auto[0] auto[2621440:3145727] auto[1] 8520 1 T8 1 T108 54 T94 1
auto[0] auto[0] auto[3145728:3670015] auto[0] 173552 1 T5 13 T7 400 T8 11394
auto[0] auto[0] auto[3145728:3670015] auto[1] 4525 1 T7 125 T8 2487 T108 1068
auto[0] auto[0] auto[3670016:4194303] auto[0] 221588 1 T5 891 T7 1 T8 4286
auto[0] auto[0] auto[3670016:4194303] auto[1] 6925 1 T8 3 T108 2652 T193 6


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 123787 1 T2 1 T4 1 T5 101
auto[0] auto[0] auto[1] 1400071 1 T5 4187 T7 2169 T8 30446

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