Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.34	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	36	92	71.88

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	36	92	71.88	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2402

1

T2

14

T4

20

T5

4

auto[1]

902

1

T70

24

T74

6

T71

16

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	350	1			T70	24		T107	14		T27	16
values[1]	470	1			T2	14		T9	2		T101	6
values[2]	444	1			T8	14		T123	2		T28	12
values[3]	412	1			T7	6		T82	8		T195	14
values[4]	466	1			T108	18		T199	2		T198	10
values[5]	376	1			T5	4		T24	12		T26	8
values[6]	244	1			T4	20		T197	2		T73	22
values[7]	542	1			T6	26		T122	34		T23	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	402	1			T197	2		T75	20		T43	4
values[1]	346	1			T101	6		T195	14		T215	16
values[2]	340	1			T7	6		T122	34		T42	26
values[3]	444	1			T4	20		T5	4		T23	2
values[4]	454	1			T6	26		T107	14		T199	2
values[5]	498	1			T2	14		T70	24		T123	2
values[6]	436	1			T8	14		T205	22		T224	8
values[7]	384	1			T9	2		T194	8		T259	2

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	36	92	71.88	36

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[2] , values[3]]	[values[0]]	--	--	2
[auto[0]]	[values[6]]	[values[5]]	0	1	1
[auto[1]]	[values[0]]	[values[0]]	0	1	1
[auto[1]]	[values[0]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[0]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[1]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[1]]	[values[4]]	0	1	1
[auto[1]]	[values[1]]	[values[6]]	0	1	1
[auto[1]]	[values[2]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[2]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[3]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[3]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[4]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[4]]	[values[7]]	0	1	1
[auto[1]]	[values[5]]	[values[1]]	0	1	1
[auto[1]]	[values[5]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[6]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[6]]	[values[4]]	0	1	1
[auto[1]]	[values[6]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[7]]	[values[1]]	0	1	1
[auto[1]]	[values[7]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[7]]	[values[7]]	0	1	1

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	58	1			T94	10		T98	24		T280	6
auto[0]	values[0]	values[1]	12	1			T97	12		-	-		-	-
auto[0]	values[0]	values[2]	34	1			T235	2		T326	18		T327	14
auto[0]	values[0]	values[3]	60	1			T287	18		T90	2		T268	32
auto[0]	values[0]	values[4]	56	1			T107	14		T25	14		T289	28
auto[0]	values[0]	values[5]	22	1			T27	16		T227	6		-	-
auto[0]	values[0]	values[6]	10	1			T79	10		-	-		-	-
auto[0]	values[0]	values[7]	22	1			T293	18		T276	4		-	-
auto[0]	values[1]	values[0]	74	1			T229	22		T128	24		T283	26
auto[0]	values[1]	values[1]	14	1			T101	6		T93	2		T253	4
auto[0]	values[1]	values[2]	30	1			T42	26		T103	2		T328	2
auto[0]	values[1]	values[3]	32	1			T111	20		T206	10		T181	2
auto[0]	values[1]	values[4]	20	1			T265	2		T258	16		T285	2
auto[0]	values[1]	values[5]	38	1			T2	14		T113	20		T184	4
auto[0]	values[1]	values[6]	44	1			T205	22		T329	2		T192	20
auto[0]	values[1]	values[7]	54	1			T9	2		T213	14		T54	24
auto[0]	values[2]	values[1]	34	1			T104	8		T330	14		T331	12
auto[0]	values[2]	values[2]	70	1			T28	12		T230	16		T297	10
auto[0]	values[2]	values[3]	52	1			T332	16		T245	4		T333	32
auto[0]	values[2]	values[4]	50	1			T334	18		T204	32		-	-
auto[0]	values[2]	values[5]	48	1			T123	2		T78	8		T278	26
auto[0]	values[2]	values[6]	90	1			T8	14		T189	26		T202	30
auto[0]	values[2]	values[7]	22	1			T208	4		T335	12		T302	6
auto[0]	values[3]	values[1]	52	1			T195	14		T211	6		T249	6
auto[0]	values[3]	values[2]	32	1			T7	6		T82	8		T234	18
auto[0]	values[3]	values[3]	64	1			T274	28		T105	16		T306	20
auto[0]	values[3]	values[4]	54	1			T207	24		T336	30		-	-
auto[0]	values[3]	values[5]	42	1			T337	12		T255	18		T338	12
auto[0]	values[3]	values[6]	24	1			T190	6		T300	12		T339	6
auto[0]	values[3]	values[7]	36	1			T246	26		T129	2		T340	8
auto[0]	values[4]	values[0]	40	1			T298	24		T341	2		T237	14
auto[0]	values[4]	values[1]	30	1			T269	26		T210	4		-	-
auto[0]	values[4]	values[2]	40	1			T77	26		T342	10		T252	4
auto[0]	values[4]	values[3]	24	1			T261	10		T296	10		T217	4
auto[0]	values[4]	values[4]	46	1			T199	2		T198	10		T193	16
auto[0]	values[4]	values[5]	100	1			T108	18		T102	6		T272	40
auto[0]	values[4]	values[6]	12	1			T224	8		T291	4		-	-
auto[0]	values[4]	values[7]	22	1			T194	8		T220	10		T201	4
auto[0]	values[5]	values[0]	22	1			T75	20		T236	2		-	-
auto[0]	values[5]	values[1]	84	1			T260	4		T343	14		T223	22
auto[0]	values[5]	values[2]	26	1			T45	4		T344	22		-	-
auto[0]	values[5]	values[3]	18	1			T5	4		T26	8		T110	2
auto[0]	values[5]	values[4]	44	1			T345	26		T130	18		-	-
auto[0]	values[5]	values[5]	32	1			T24	12		T346	20		-	-
auto[0]	values[5]	values[6]	14	1			T347	14		-	-		-	-
auto[0]	values[5]	values[7]	20	1			T348	4		T349	16		-	-
auto[0]	values[6]	values[0]	2	1			T197	2		-	-		-	-
auto[0]	values[6]	values[1]	30	1			T96	22		T350	8		-	-
auto[0]	values[6]	values[2]	22	1			T266	12		T351	10		-	-
auto[0]	values[6]	values[3]	26	1			T4	20		T240	6		-	-
auto[0]	values[6]	values[4]	30	1			T231	2		T225	22		T352	6
auto[0]	values[6]	values[6]	32	1			T353	6		T277	20		T187	2
auto[0]	values[6]	values[7]	26	1			T354	8		T355	18		-	-
auto[0]	values[7]	values[0]	32	1			T43	4		T250	16		T264	8
auto[0]	values[7]	values[1]	58	1			T215	16		T76	4		T203	2
auto[0]	values[7]	values[2]	40	1			T122	34		T196	6		-	-
auto[0]	values[7]	values[3]	22	1			T23	2		T109	2		T112	18
auto[0]	values[7]	values[4]	86	1			T6	26		T44	12		T290	24
auto[0]	values[7]	values[5]	60	1			T191	14		T301	10		T305	36
auto[0]	values[7]	values[6]	46	1			T242	32		T267	4		T254	10
auto[0]	values[7]	values[7]	66	1			T259	2		T356	34		T307	30
auto[1]	values[0]	values[1]	32	1			T80	32		-	-		-	-
auto[1]	values[0]	values[2]	4	1			T51	4		-	-		-	-
auto[1]	values[0]	values[5]	40	1			T70	24		T84	16		-	-
auto[1]	values[1]	values[0]	46	1			T87	26		T212	20		-	-
auto[1]	values[1]	values[3]	26	1			T357	26		-	-		-	-
auto[1]	values[1]	values[5]	36	1			T74	6		T81	30		-	-
auto[1]	values[1]	values[7]	56	1			T243	28		T222	28		-	-
auto[1]	values[2]	values[3]	34	1			T257	30		T219	4		-	-
auto[1]	values[2]	values[6]	20	1			T358	20		-	-		-	-
auto[1]	values[2]	values[7]	24	1			T238	8		T359	16		-	-
auto[1]	values[3]	values[0]	18	1			T83	18		-	-		-	-
auto[1]	values[3]	values[3]	42	1			T105	4		T360	38		-	-
auto[1]	values[3]	values[6]	34	1			T273	14		T263	20		-	-
auto[1]	values[3]	values[7]	14	1			T304	14		-	-		-	-
auto[1]	values[4]	values[0]	32	1			T71	16		T86	16		-	-
auto[1]	values[4]	values[3]	18	1			T284	18		-	-		-	-
auto[1]	values[4]	values[4]	68	1			T275	22		T85	32		T361	14
auto[1]	values[4]	values[5]	6	1			T226	6		-	-		-	-
auto[1]	values[4]	values[6]	28	1			T72	28		-	-		-	-
auto[1]	values[5]	values[0]	24	1			T232	16		T294	8		-	-
auto[1]	values[5]	values[2]	22	1			T91	12		T362	10		-	-
auto[1]	values[5]	values[5]	30	1			T271	30		-	-		-	-
auto[1]	values[5]	values[6]	18	1			T221	18		-	-		-	-
auto[1]	values[5]	values[7]	22	1			T363	22		-	-		-	-
auto[1]	values[6]	values[0]	26	1			T244	26		-	-		-	-
auto[1]	values[6]	values[3]	26	1			T303	26		-	-		-	-
auto[1]	values[6]	values[5]	24	1			T73	22		T182	2		-	-
auto[1]	values[7]	values[0]	28	1			T364	18		T299	10		-	-
auto[1]	values[7]	values[2]	20	1			T239	20		-	-		-	-
auto[1]	values[7]	values[5]	20	1			T365	4		T214	16		-	-
auto[1]	values[7]	values[6]	64	1			T209	12		T200	30		T218	18