Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
dashboard | hierarchy | modlist | groups | tests | asserts


Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 66 0 66 100.00
Crosses 128 0 128 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_filtered 2 0 2 100.00 100 1 1 2
cp_opcode 64 0 64 100.00 100 1 1 64


Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 128 0 128 100.00 100 1 1 0


Summary for Variable cp_filtered

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_filtered

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1653 1 T2 7 T4 10 T5 2
auto[1] 2271 1 T2 7 T4 10 T5 2



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 64 0 64 100.00


Automatically Generated Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:3] 336 1 T2 2 T6 6 T7 2
auto[4:7] 289 1 T6 4 T7 2 T8 8
auto[8:11] 276 1 T2 2 T4 6 T6 2
auto[12:15] 10 1 T213 2 T364 2 T204 2
auto[16:19] 14 1 T243 2 T214 2 T283 2
auto[20:23] 196 1 T4 2 T6 2 T8 6
auto[24:27] 14 1 T77 2 T208 2 T354 2
auto[28:31] 17 1 T232 2 T268 2 T105 3
auto[32:35] 16 1 T72 6 T222 2 T281 2
auto[36:39] 34 1 T6 4 T91 2 T238 2
auto[40:43] 26 1 T198 4 T75 4 T205 8
auto[44:47] 22 1 T195 2 T74 2 T77 2
auto[48:51] 10 1 T229 4 T83 2 T223 2
auto[52:55] 202 1 T70 4 T122 12 T107 6
auto[56:59] 326 1 T4 2 T10 3 T70 2
auto[60:63] 8 1 T76 2 T283 2 T336 2
auto[64:67] 18 1 T195 2 T75 4 T229 2
auto[68:71] 33 1 T82 2 T91 2 T274 4
auto[72:75] 8 1 T205 2 T364 2 T239 4
auto[76:79] 19 1 T257 2 T354 4 T204 2
auto[80:83] 2 1 T229 2 - - - -
auto[84:87] 8 1 T206 4 T226 2 T86 2
auto[88:91] 142 1 T107 2 T108 2 T224 2
auto[92:95] 28 1 T78 2 T80 2 T289 2
auto[96:99] 8 1 T73 2 T361 4 T303 2
auto[100:103] 12 1 T75 4 T27 2 T223 2
auto[104:107] 284 1 T2 6 T4 2 T99 1
auto[108:111] 14 1 T205 4 T218 2 T85 2
auto[112:115] 16 1 T273 2 T218 2 T283 2
auto[116:119] 2 1 T200 2 - - - -
auto[120:123] 22 1 T244 2 T213 6 T200 2
auto[124:127] 2 1 T361 2 - - - -
auto[128:131] 15 1 T42 4 T255 2 T105 1
auto[132:135] 26 1 T243 2 T80 6 T222 2
auto[136:139] 14 1 T80 4 T200 2 T220 2
auto[140:143] 25 1 T4 2 T81 2 T209 4
auto[144:147] 24 1 T70 6 T72 4 T81 2
auto[148:151] 10 1 T194 2 T72 2 T209 2
auto[152:155] 20 1 T70 4 T80 2 T221 2
auto[156:159] 242 1 T2 2 T6 6 T9 2
auto[160:163] 18 1 T244 2 T356 6 T263 4
auto[164:167] 4 1 T243 2 T202 2 - -
auto[168:171] 14 1 T4 2 T26 2 T27 4
auto[172:175] 18 1 T77 6 T275 4 T257 4
auto[176:179] 20 1 T343 4 T200 2 T258 2
auto[180:183] 89 1 T5 4 T24 4 T26 2
auto[184:187] 317 1 T4 4 T6 2 T7 2
auto[188:191] 22 1 T2 2 T242 4 T278 2
auto[192:195] 30 1 T79 4 T222 2 T278 4
auto[196:199] 26 1 T354 2 T54 6 T356 2
auto[200:203] 22 1 T241 2 T84 2 T268 2
auto[204:207] 12 1 T27 2 T215 2 T81 2
auto[208:211] 12 1 T70 2 T274 2 T326 2
auto[212:215] 16 1 T213 2 T275 4 T273 2
auto[216:219] 14 1 T266 2 T218 2 T347 2
auto[220:223] 14 1 T261 2 T54 2 T85 2
auto[224:227] 25 1 T73 6 T257 6 T214 2
auto[228:231] 18 1 T102 2 T75 2 T215 2
auto[232:235] 353 1 T70 2 T124 2 T198 4
auto[236:239] 38 1 T195 2 T229 2 T242 6
auto[240:243] 10 1 T76 2 T218 2 T223 2
auto[244:247] 8 1 T242 4 T336 2 T284 2
auto[248:251] 18 1 T274 2 T365 2 T218 2
auto[252:255] 16 1 T77 4 T343 2 T200 6



Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_opcodecp_filteredCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:3] auto[0] 123 1 T2 1 T6 3 T7 1
auto[0:3] auto[1] 213 1 T2 1 T6 3 T7 1
auto[4:7] auto[0] 144 1 T6 2 T7 1 T8 4
auto[4:7] auto[1] 145 1 T6 2 T7 1 T8 4
auto[8:11] auto[0] 93 1 T2 1 T4 3 T6 1
auto[8:11] auto[1] 183 1 T2 1 T4 3 T6 1
auto[12:15] auto[0] 5 1 T213 1 T364 1 T204 1
auto[12:15] auto[1] 5 1 T213 1 T364 1 T204 1
auto[16:19] auto[0] 7 1 T243 1 T214 1 T283 1
auto[16:19] auto[1] 7 1 T243 1 T214 1 T283 1
auto[20:23] auto[0] 98 1 T4 1 T6 1 T8 3
auto[20:23] auto[1] 98 1 T4 1 T6 1 T8 3
auto[24:27] auto[0] 7 1 T77 1 T208 1 T354 1
auto[24:27] auto[1] 7 1 T77 1 T208 1 T354 1
auto[28:31] auto[0] 10 1 T232 1 T268 1 T105 3
auto[28:31] auto[1] 7 1 T232 1 T268 1 T345 2
auto[32:35] auto[0] 8 1 T72 3 T222 1 T281 1
auto[32:35] auto[1] 8 1 T72 3 T222 1 T281 1
auto[36:39] auto[0] 17 1 T6 2 T91 1 T238 1
auto[36:39] auto[1] 17 1 T6 2 T91 1 T238 1
auto[40:43] auto[0] 13 1 T198 2 T75 2 T205 4
auto[40:43] auto[1] 13 1 T198 2 T75 2 T205 4
auto[44:47] auto[0] 11 1 T195 1 T74 1 T77 1
auto[44:47] auto[1] 11 1 T195 1 T74 1 T77 1
auto[48:51] auto[0] 5 1 T229 2 T83 1 T223 1
auto[48:51] auto[1] 5 1 T229 2 T83 1 T223 1
auto[52:55] auto[0] 101 1 T70 2 T122 6 T107 3
auto[52:55] auto[1] 101 1 T70 2 T122 6 T107 3
auto[56:59] auto[0] 111 1 T4 1 T70 1 T195 2
auto[56:59] auto[1] 215 1 T4 1 T10 3 T70 1
auto[60:63] auto[0] 4 1 T76 1 T283 1 T336 1
auto[60:63] auto[1] 4 1 T76 1 T283 1 T336 1
auto[64:67] auto[0] 9 1 T195 1 T75 2 T229 1
auto[64:67] auto[1] 9 1 T195 1 T75 2 T229 1
auto[68:71] auto[0] 17 1 T82 1 T91 1 T274 2
auto[68:71] auto[1] 16 1 T82 1 T91 1 T274 2
auto[72:75] auto[0] 4 1 T205 1 T364 1 T239 2
auto[72:75] auto[1] 4 1 T205 1 T364 1 T239 2
auto[76:79] auto[0] 10 1 T257 1 T354 2 T204 1
auto[76:79] auto[1] 9 1 T257 1 T354 2 T204 1
auto[80:83] auto[0] 1 1 T229 1 - - - -
auto[80:83] auto[1] 1 1 T229 1 - - - -
auto[84:87] auto[0] 4 1 T206 2 T226 1 T86 1
auto[84:87] auto[1] 4 1 T206 2 T226 1 T86 1
auto[88:91] auto[0] 71 1 T107 1 T108 1 T224 1
auto[88:91] auto[1] 71 1 T107 1 T108 1 T224 1
auto[92:95] auto[0] 14 1 T78 1 T80 1 T289 1
auto[92:95] auto[1] 14 1 T78 1 T80 1 T289 1
auto[96:99] auto[0] 4 1 T73 1 T361 2 T303 1
auto[96:99] auto[1] 4 1 T73 1 T361 2 T303 1
auto[100:103] auto[0] 6 1 T75 2 T27 1 T223 1
auto[100:103] auto[1] 6 1 T75 2 T27 1 T223 1
auto[104:107] auto[0] 87 1 T2 3 T4 1 T42 3
auto[104:107] auto[1] 197 1 T2 3 T4 1 T99 1
auto[108:111] auto[0] 7 1 T205 2 T218 1 T85 1
auto[108:111] auto[1] 7 1 T205 2 T218 1 T85 1
auto[112:115] auto[0] 8 1 T273 1 T218 1 T283 1
auto[112:115] auto[1] 8 1 T273 1 T218 1 T283 1
auto[116:119] auto[0] 1 1 T200 1 - - - -
auto[116:119] auto[1] 1 1 T200 1 - - - -
auto[120:123] auto[0] 11 1 T244 1 T213 3 T200 1
auto[120:123] auto[1] 11 1 T244 1 T213 3 T200 1
auto[124:127] auto[0] 1 1 T361 1 - - - -
auto[124:127] auto[1] 1 1 T361 1 - - - -
auto[128:131] auto[0] 7 1 T42 2 T255 1 T237 2
auto[128:131] auto[1] 8 1 T42 2 T255 1 T105 1
auto[132:135] auto[0] 13 1 T243 1 T80 3 T222 1
auto[132:135] auto[1] 13 1 T243 1 T80 3 T222 1
auto[136:139] auto[0] 7 1 T80 2 T200 1 T220 1
auto[136:139] auto[1] 7 1 T80 2 T200 1 T220 1
auto[140:143] auto[0] 12 1 T4 1 T81 1 T209 2
auto[140:143] auto[1] 13 1 T4 1 T81 1 T209 2
auto[144:147] auto[0] 12 1 T70 3 T72 2 T81 1
auto[144:147] auto[1] 12 1 T70 3 T72 2 T81 1
auto[148:151] auto[0] 5 1 T194 1 T72 1 T209 1
auto[148:151] auto[1] 5 1 T194 1 T72 1 T209 1
auto[152:155] auto[0] 10 1 T70 2 T80 1 T221 1
auto[152:155] auto[1] 10 1 T70 2 T80 1 T221 1
auto[156:159] auto[0] 120 1 T2 1 T6 3 T9 1
auto[156:159] auto[1] 122 1 T2 1 T6 3 T9 1
auto[160:163] auto[0] 9 1 T244 1 T356 3 T263 2
auto[160:163] auto[1] 9 1 T244 1 T356 3 T263 2
auto[164:167] auto[0] 2 1 T243 1 T202 1 - -
auto[164:167] auto[1] 2 1 T243 1 T202 1 - -
auto[168:171] auto[0] 7 1 T4 1 T26 1 T27 2
auto[168:171] auto[1] 7 1 T4 1 T26 1 T27 2
auto[172:175] auto[0] 9 1 T77 3 T275 2 T257 2
auto[172:175] auto[1] 9 1 T77 3 T275 2 T257 2
auto[176:179] auto[0] 10 1 T343 2 T200 1 T258 1
auto[176:179] auto[1] 10 1 T343 2 T200 1 T258 1
auto[180:183] auto[0] 45 1 T5 2 T24 2 T26 1
auto[180:183] auto[1] 44 1 T5 2 T24 2 T26 1
auto[184:187] auto[0] 101 1 T4 2 T6 1 T7 1
auto[184:187] auto[1] 216 1 T4 2 T6 1 T7 1
auto[188:191] auto[0] 11 1 T2 1 T242 2 T278 1
auto[188:191] auto[1] 11 1 T2 1 T242 2 T278 1
auto[192:195] auto[0] 15 1 T79 2 T222 1 T278 2
auto[192:195] auto[1] 15 1 T79 2 T222 1 T278 2
auto[196:199] auto[0] 13 1 T354 1 T54 3 T356 1
auto[196:199] auto[1] 13 1 T354 1 T54 3 T356 1
auto[200:203] auto[0] 11 1 T241 1 T84 1 T268 1
auto[200:203] auto[1] 11 1 T241 1 T84 1 T268 1
auto[204:207] auto[0] 6 1 T27 1 T215 1 T81 1
auto[204:207] auto[1] 6 1 T27 1 T215 1 T81 1
auto[208:211] auto[0] 6 1 T70 1 T274 1 T326 1
auto[208:211] auto[1] 6 1 T70 1 T274 1 T326 1
auto[212:215] auto[0] 8 1 T213 1 T275 2 T273 1
auto[212:215] auto[1] 8 1 T213 1 T275 2 T273 1
auto[216:219] auto[0] 7 1 T266 1 T218 1 T347 1
auto[216:219] auto[1] 7 1 T266 1 T218 1 T347 1
auto[220:223] auto[0] 7 1 T261 1 T54 1 T85 1
auto[220:223] auto[1] 7 1 T261 1 T54 1 T85 1
auto[224:227] auto[0] 12 1 T73 3 T257 3 T214 1
auto[224:227] auto[1] 13 1 T73 3 T257 3 T214 1
auto[228:231] auto[0] 9 1 T102 1 T75 1 T215 1
auto[228:231] auto[1] 9 1 T102 1 T75 1 T215 1
auto[232:235] auto[0] 122 1 T70 1 T198 2 T75 1
auto[232:235] auto[1] 231 1 T70 1 T124 2 T198 2
auto[236:239] auto[0] 19 1 T195 1 T229 1 T242 3
auto[236:239] auto[1] 19 1 T195 1 T229 1 T242 3
auto[240:243] auto[0] 5 1 T76 1 T218 1 T223 1
auto[240:243] auto[1] 5 1 T76 1 T218 1 T223 1
auto[244:247] auto[0] 4 1 T242 2 T336 1 T284 1
auto[244:247] auto[1] 4 1 T242 2 T336 1 T284 1
auto[248:251] auto[0] 9 1 T274 1 T365 1 T218 1
auto[248:251] auto[1] 9 1 T274 1 T365 1 T218 1
auto[252:255] auto[0] 8 1 T77 2 T343 1 T200 3
auto[252:255] auto[1] 8 1 T77 2 T343 1 T200 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%