Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.63	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	1	59	98.33

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	1	59	98.33	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	88	1			T7	4		T272	2		T111	12
auto[ReadAddrCrossIntoMailbox]	50	1			T199	2		T272	2		T298	2
auto[ReadAddrCrossOutOfMailbox]	55	1			T272	14		T287	2		T298	2
auto[ReadAddrCrossAllMailbox]	36	1			T272	8		T287	2		T298	4
auto[ReadAddrOutsideMailbox]	868	1			T2	10		T4	12		T6	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

548

1

T2

5

T4

6

T6

3

auto[1]

549

1

T2

5

T4

6

T6

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	220	1			T2	2		T6	4		T7	2
read_ops[0x0b]	163	1			T2	2		T4	6		T6	2
read_ops[0x3b]	212	1			T70	2		T195	2		T27	2
read_ops[0x6b]	152	1			T2	6		T4	2		T42	6
read_ops[0xbb]	188	1			T4	4		T7	2		T101	2
read_ops[0xeb]	162	1			T70	2		T198	4		T272	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	1	59	98.33	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x03]]	[auto[ReadAddrCrossAllMailbox]]	[auto[1]]	0	1	1

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T7	1		T111	5		T44	4
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	20	1			T7	1		T111	5		T44	4
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T292	3		T105	1		-	-
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T292	3		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T292	1		T228	1		T280	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T292	1		T228	1		T280	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T105	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	81	1			T2	1		T6	2		T101	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	81	1			T2	1		T6	2		T101	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	1	1			T191	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	1	1			T191	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T249	1		T254	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T249	1		T254	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	6	1			T272	3		T254	2		T351	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	6	1			T272	3		T254	2		T351	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T280	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T280	1		T105	1		-	-
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	71	1			T2	1		T4	3		T6	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	71	1			T2	1		T4	3		T6	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	12	1			T272	1		T298	2		T228	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	12	1			T272	1		T298	2		T228	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T272	1		T290	1		T286	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T272	1		T290	1		T286	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	8	1			T272	2		T287	1		T290	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	8	1			T272	2		T287	1		T290	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T272	2		T287	1		T298	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	5	1			T272	2		T287	1		T298	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	77	1			T70	1		T195	1		T27	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	77	1			T70	1		T195	1		T27	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	3	1			T298	2		T262	1		-	-
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	3	1			T298	2		T262	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T290	2		T262	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T290	2		T262	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T298	1		T290	1		T262	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T298	1		T290	1		T262	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T298	1		T292	1		T285	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T298	1		T292	1		T285	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	64	1			T2	3		T4	1		T42	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	64	1			T2	3		T4	1		T42	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	4	1			T7	1		T298	1		T98	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	4	1			T7	1		T298	1		T98	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	11	1			T199	1		T298	1		T290	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	12	1			T199	1		T298	1		T290	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T272	1		T353	1		T280	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T272	1		T353	1		T280	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	6	1			T272	2		T353	1		T262	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	6	1			T272	2		T353	1		T262	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	69	1			T4	2		T101	1		T42	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	69	1			T4	2		T101	1		T42	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	4	1			T111	1		T306	3		-	-
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	4	1			T111	1		T306	3		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T292	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T292	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T272	1		T292	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T272	1		T292	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T290	2		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T290	2		-	-		-	-
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	72	1			T70	1		T198	2		T287	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	72	1			T70	1		T198	2		T287	2