Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	324877	1			T1	3779		T2	232		T12	7128
all_pins[1]	324877	1			T1	3779		T2	232		T12	7128
all_pins[2]	324877	1			T1	3779		T2	232		T12	7128
all_pins[3]	324877	1			T1	3779		T2	232		T12	7128
all_pins[4]	324877	1			T1	3779		T2	232		T12	7128
all_pins[5]	324877	1			T1	3779		T2	232		T12	7128
all_pins[6]	324877	1			T1	3779		T2	232		T12	7128
all_pins[7]	324877	1			T1	3779		T2	232		T12	7128

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2597975	1			T1	30232		T2	1856		T12	57024
values[0x1]	1041	1			T18	11		T31	34		T32	27
transitions[0x0=>0x1]	771	1			T18	7		T31	24		T32	24
transitions[0x1=>0x0]	781	1			T18	7		T31	24		T32	24

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	324750	1			T1	3779		T2	232		T12	7128
all_pins[0]	values[0x1]	127	1			T18	3		T31	8		T32	2
all_pins[0]	transitions[0x0=>0x1]	87	1			T18	2		T31	5		T32	2
all_pins[0]	transitions[0x1=>0x0]	97	1			T38	3		T52	4		T375	4
all_pins[1]	values[0x0]	324740	1			T1	3779		T2	232		T12	7128
all_pins[1]	values[0x1]	137	1			T18	1		T31	3		T38	5
all_pins[1]	transitions[0x0=>0x1]	98	1			T31	2		T38	4		T52	6
all_pins[1]	transitions[0x1=>0x0]	89	1			T18	2		T31	2		T32	5
all_pins[2]	values[0x0]	324749	1			T1	3779		T2	232		T12	7128
all_pins[2]	values[0x1]	128	1			T18	3		T31	3		T32	5
all_pins[2]	transitions[0x0=>0x1]	99	1			T18	3		T31	3		T32	5
all_pins[2]	transitions[0x1=>0x0]	78	1			T31	5		T32	3		T38	5
all_pins[3]	values[0x0]	324770	1			T1	3779		T2	232		T12	7128
all_pins[3]	values[0x1]	107	1			T31	5		T32	3		T38	7
all_pins[3]	transitions[0x0=>0x1]	79	1			T31	4		T32	3		T38	6
all_pins[3]	transitions[0x1=>0x0]	117	1			T18	2		T31	1		T32	2
all_pins[4]	values[0x0]	324732	1			T1	3779		T2	232		T12	7128
all_pins[4]	values[0x1]	145	1			T18	2		T31	2		T32	2
all_pins[4]	transitions[0x0=>0x1]	120	1			T18	2		T31	2		T32	2
all_pins[4]	transitions[0x1=>0x0]	92	1			T31	4		T32	2		T38	3
all_pins[5]	values[0x0]	324760	1			T1	3779		T2	232		T12	7128
all_pins[5]	values[0x1]	117	1			T31	4		T32	2		T38	5
all_pins[5]	transitions[0x0=>0x1]	88	1			T31	2		T32	2		T38	3
all_pins[5]	transitions[0x1=>0x0]	105	1			T31	3		T32	7		T38	5
all_pins[6]	values[0x0]	324743	1			T1	3779		T2	232		T12	7128
all_pins[6]	values[0x1]	134	1			T31	5		T32	7		T38	7
all_pins[6]	transitions[0x0=>0x1]	100	1			T31	4		T32	5		T38	7
all_pins[6]	transitions[0x1=>0x0]	112	1			T18	2		T31	3		T32	4
all_pins[7]	values[0x0]	324731	1			T1	3779		T2	232		T12	7128
all_pins[7]	values[0x1]	146	1			T18	2		T31	4		T32	6
all_pins[7]	transitions[0x0=>0x1]	100	1			T31	2		T32	5		T38	5
all_pins[7]	transitions[0x1=>0x0]	91	1			T18	1		T31	6		T32	1