Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
64.38	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	52	76	59.38

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	52	76	59.38	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	416	1			T101	6		T42	26		T108	18
values[1]	530	1			T9	2		T24	12		T194	8
values[2]	426	1			T102	6		T195	14		T196	6
values[3]	334	1			T5	4		T6	26		T91	12
values[4]	342	1			T82	8		T103	2		T75	20
values[5]	450	1			T2	14		T123	2		T197	2
values[6]	382	1			T4	20		T7	6		T8	14
values[7]	424	1			T122	34		T107	14		T23	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	468	1			T6	26		T82	8		T198	10
values[1]	514	1			T2	14		T5	4		T7	6
values[2]	418	1			T107	14		T24	12		T103	2
values[3]	262	1			T70	24		T122	34		T101	6
values[4]	378	1			T9	2		T108	18		T194	8
values[5]	482	1			T199	2		T27	16		T78	8
values[6]	366	1			T42	26		T26	8		T74	6
values[7]	416	1			T4	20		T195	14		T28	12

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3250

1

T2

14

T4

20

T5

4

auto[1]

54

1

T71

4

T72

2

T73

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	52	76	59.38	52

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[3]]	[values[6]]	0	1	1
[auto[1]]	[values[1]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[1]]	[values[3] , values[4] , values[5]]	--	--	3
[auto[1]]	[values[1]]	[values[7]]	0	1	1
[auto[1]]	[values[2]]	[values[2] , values[3] , values[4] , values[5]]	--	--	4
[auto[1]]	[values[2]]	[values[7]]	0	1	1
[auto[1]]	[values[3]]	[values[0] , values[1] , values[2] , values[3] , values[4]]	--	--	5
[auto[1]]	[values[3]]	[values[6]]	0	1	1
[auto[1]]	[values[4] , values[5]]	[values[0] , values[1] , values[2] , values[3]]	--	--	8
[auto[1]]	[values[4] , values[5]]	[values[5] , values[6]]	--	--	4
[auto[1]]	[values[6]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	6
[auto[1]]	[values[6]]	[values[7]]	0	1	1
[auto[1]]	[values[7]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[7]]	[values[5] , values[6] , values[7]]	--	--	3

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	64	1			T200	30		T201	4		T202	30
auto[0]	values[0]	values[1]	114	1			T25	14		T203	2		T204	32
auto[0]	values[0]	values[2]	32	1			T205	22		T206	10		-	-
auto[0]	values[0]	values[3]	30	1			T101	6		T207	24		-	-
auto[0]	values[0]	values[4]	20	1			T108	18		T129	2		-	-
auto[0]	values[0]	values[5]	62	1			T199	2		T208	4		T209	12
auto[0]	values[0]	values[6]	68	1			T42	26		T26	8		T210	4
auto[0]	values[0]	values[7]	26	1			T211	6		T212	20		-	-
auto[0]	values[1]	values[0]	114	1			T213	14		T112	18		T214	16
auto[0]	values[1]	values[1]	44	1			T215	16		T216	10		T217	4
auto[0]	values[1]	values[2]	30	1			T24	12		T43	4		T86	14
auto[0]	values[1]	values[3]	24	1			T90	2		T218	18		T219	4
auto[0]	values[1]	values[4]	110	1			T9	2		T194	8		T128	24
auto[0]	values[1]	values[5]	62	1			T98	24		T220	10		T221	18
auto[0]	values[1]	values[6]	78	1			T74	6		T222	28		T223	22
auto[0]	values[1]	values[7]	60	1			T224	8		T193	16		T225	22
auto[0]	values[2]	values[0]	32	1			T72	26		T226	6		-	-
auto[0]	values[2]	values[1]	66	1			T227	6		T83	14		T228	20
auto[0]	values[2]	values[2]	150	1			T96	22		T229	22		T189	26
auto[0]	values[2]	values[3]	6	1			T102	6		-	-		-	-
auto[0]	values[2]	values[4]	62	1			T196	6		T230	16		T231	2
auto[0]	values[2]	values[5]	50	1			T232	16		T233	16		T234	18
auto[0]	values[2]	values[6]	20	1			T235	2		T87	18		-	-
auto[0]	values[2]	values[7]	26	1			T195	14		T110	2		T190	6
auto[0]	values[3]	values[0]	82	1			T6	26		T236	2		T237	14
auto[0]	values[3]	values[1]	14	1			T5	4		T109	2		T238	8
auto[0]	values[3]	values[2]	20	1			T239	20		-	-		-	-
auto[0]	values[3]	values[3]	10	1			T51	4		T240	6		-	-
auto[0]	values[3]	values[4]	38	1			T241	6		T242	32		-	-
auto[0]	values[3]	values[5]	92	1			T91	12		T243	28		T244	26
auto[0]	values[3]	values[7]	68	1			T73	16		T245	4		T246	26
auto[0]	values[4]	values[0]	14	1			T82	8		T247	4		T187	2
auto[0]	values[4]	values[1]	116	1			T94	10		T97	12		T248	6
auto[0]	values[4]	values[2]	34	1			T103	2		T75	20		T249	6
auto[0]	values[4]	values[3]	26	1			T250	16		T251	10		-	-
auto[0]	values[4]	values[4]	36	1			T85	28		T252	4		T253	4
auto[0]	values[4]	values[5]	50	1			T254	10		T255	18		T256	2
auto[0]	values[4]	values[6]	14	1			T79	10		T45	4		-	-
auto[0]	values[4]	values[7]	40	1			T80	24		T191	14		T182	2
auto[0]	values[5]	values[0]	48	1			T197	2		T257	30		T258	16
auto[0]	values[5]	values[1]	20	1			T2	14		T259	2		T260	4
auto[0]	values[5]	values[2]	40	1			T261	10		T262	10		T263	20
auto[0]	values[5]	values[3]	36	1			T123	2		T264	8		T265	2
auto[0]	values[5]	values[4]	50	1			T71	12		T104	8		T266	12
auto[0]	values[5]	values[5]	70	1			T27	16		T267	4		T268	32
auto[0]	values[5]	values[6]	76	1			T269	26		T270	20		T271	30
auto[0]	values[5]	values[7]	104	1			T28	12		T272	40		T273	14
auto[0]	values[6]	values[0]	78	1			T274	28		T275	22		T276	4
auto[0]	values[6]	values[1]	76	1			T7	6		T8	14		T277	20
auto[0]	values[6]	values[2]	68	1			T76	4		T278	26		T279	28
auto[0]	values[6]	values[3]	32	1			T70	24		T280	6		T281	2
auto[0]	values[6]	values[4]	2	1			T282	2		-	-		-	-
auto[0]	values[6]	values[5]	52	1			T78	8		T283	26		T284	18
auto[0]	values[6]	values[6]	46	1			T81	28		T184	4		T285	2
auto[0]	values[6]	values[7]	26	1			T4	20		T286	6		-	-
auto[0]	values[7]	values[0]	34	1			T198	10		T287	18		T288	6
auto[0]	values[7]	values[1]	60	1			T111	20		T44	12		T289	28
auto[0]	values[7]	values[2]	42	1			T107	14		T290	24		T291	4
auto[0]	values[7]	values[3]	98	1			T122	34		T23	2		T292	30
auto[0]	values[7]	values[4]	50	1			T77	26		T293	18		T294	6
auto[0]	values[7]	values[5]	40	1			T295	2		T296	10		T297	10
auto[0]	values[7]	values[6]	48	1			T93	2		T298	24		T299	10
auto[0]	values[7]	values[7]	50	1			T300	12		T301	10		T302	6
auto[1]	values[1]	values[2]	2	1			T86	2		-	-		-	-
auto[1]	values[1]	values[6]	6	1			T303	6		-	-		-	-
auto[1]	values[2]	values[0]	2	1			T72	2		-	-		-	-
auto[1]	values[2]	values[1]	4	1			T83	4		-	-		-	-
auto[1]	values[2]	values[6]	8	1			T87	8		-	-		-	-
auto[1]	values[3]	values[5]	4	1			T304	4		-	-		-	-
auto[1]	values[3]	values[7]	6	1			T73	6		-	-		-	-
auto[1]	values[4]	values[4]	4	1			T85	4		-	-		-	-
auto[1]	values[4]	values[7]	8	1			T80	8		-	-		-	-
auto[1]	values[5]	values[4]	4	1			T71	4		-	-		-	-
auto[1]	values[5]	values[7]	2	1			T84	2		-	-		-	-
auto[1]	values[6]	values[6]	2	1			T81	2		-	-		-	-
auto[1]	values[7]	values[4]	2	1			T294	2		-	-		-	-