Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1507

1

T1

10

T12

2

T13

14

auto[1]

1458

1

T1

14

T13

16

T19

4

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

746

1

T1

24

T12

2

T13

25

auto[1]

2219

1

T13

5

T19

4

T20

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2679

1

T1

15

T12

2

T13

19

auto[1]

286

1

T1

9

T13

11

T20

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	588	1			T1	5		T12	2		T13	7
valid[1]	623	1			T1	2		T13	5		T20	4
valid[2]	576	1			T1	5		T13	7		T20	2
valid[3]	568	1			T1	8		T13	2		T19	1
valid[4]	610	1			T1	4		T13	9		T19	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	40	1			T1	1		T12	2		T63	4
auto[0]	auto[0]	valid[0]	auto[1]	228	1			T13	1		T21	1		T61	9
auto[0]	auto[0]	valid[1]	auto[0]	47	1			T13	1		T63	1		T69	1
auto[0]	auto[0]	valid[1]	auto[1]	240	1			T13	1		T20	1		T60	9
auto[0]	auto[0]	valid[2]	auto[0]	46	1			T1	4		T20	1		T63	5
auto[0]	auto[0]	valid[2]	auto[1]	209	1			T13	1		T60	2		T61	6
auto[0]	auto[0]	valid[3]	auto[0]	36	1			T1	2		T63	2		T69	1
auto[0]	auto[0]	valid[3]	auto[1]	229	1			T60	5		T61	4		T62	1
auto[0]	auto[0]	valid[4]	auto[0]	46	1			T13	1		T63	2		T68	2
auto[0]	auto[0]	valid[4]	auto[1]	252	1			T13	1		T60	4		T61	3
auto[0]	auto[1]	valid[0]	auto[0]	45	1			T1	2		T13	1		T63	2
auto[0]	auto[1]	valid[0]	auto[1]	227	1			T13	1		T60	2		T61	9
auto[0]	auto[1]	valid[1]	auto[0]	44	1			T1	1		T13	2		T20	1
auto[0]	auto[1]	valid[1]	auto[1]	225	1			T21	1		T60	5		T61	3
auto[0]	auto[1]	valid[2]	auto[0]	56	1			T1	1		T13	2		T20	1
auto[0]	auto[1]	valid[2]	auto[1]	209	1			T60	8		T61	7		T62	5
auto[0]	auto[1]	valid[3]	auto[0]	44	1			T1	1		T13	2		T63	4
auto[0]	auto[1]	valid[3]	auto[1]	197	1			T19	1		T60	3		T61	4
auto[0]	auto[1]	valid[4]	auto[0]	56	1			T1	3		T13	5		T63	4
auto[0]	auto[1]	valid[4]	auto[1]	203	1			T19	3		T60	3		T61	6
auto[1]	auto[0]	valid[0]	auto[0]	22	1			T1	1		T13	4		T69	1
auto[1]	auto[0]	valid[1]	auto[0]	25	1			T1	1		T13	1		T63	1
auto[1]	auto[0]	valid[2]	auto[0]	28	1			T13	2		T63	1		T68	1
auto[1]	auto[0]	valid[3]	auto[0]	27	1			T63	1		T66	1		T69	1
auto[1]	auto[0]	valid[4]	auto[0]	32	1			T1	1		T13	1		T20	1
auto[1]	auto[1]	valid[0]	auto[0]	26	1			T1	1		T63	1		T68	1
auto[1]	auto[1]	valid[1]	auto[0]	42	1			T20	2		T63	2		T68	2
auto[1]	auto[1]	valid[2]	auto[0]	28	1			T13	2		T69	1		T398	1
auto[1]	auto[1]	valid[3]	auto[0]	35	1			T1	5		T63	1		T66	1
auto[1]	auto[1]	valid[4]	auto[0]	21	1			T13	1		T69	2		T387	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal