Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19082

1

T1

698

T12

17

T13

462

auto[1]

21256

1

T13

52

T19

4

T20

20

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33106

1

T1

452

T12

8

T13

321

auto[1]

7232

1

T1

246

T12

9

T13

193

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	20909	1			T1	363		T12	10		T13	274
others[1]	3375	1			T1	59		T12	1		T13	37
others[2]	3441	1			T1	62		T12	1		T13	34
others[3]	3719	1			T1	56		T12	2		T13	53
interest[1]	2215	1			T1	43		T13	34		T20	12
interest[4]	13759	1			T1	254		T12	7		T13	172
interest[64]	6679	1			T1	115		T12	3		T13	82

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	6087	1			T1	230		T12	5		T13	142
auto[0]	auto[0]	others[1]	933	1			T1	48		T13	20		T20	9
auto[0]	auto[0]	others[2]	1015	1			T1	36		T12	1		T13	12
auto[0]	auto[0]	others[3]	1123	1			T1	37		T12	1		T13	31
auto[0]	auto[0]	interest[1]	649	1			T1	32		T13	16		T20	5
auto[0]	auto[0]	interest[4]	3970	1			T1	161		T12	4		T13	87
auto[0]	auto[0]	interest[64]	2043	1			T1	69		T12	1		T13	48
auto[0]	auto[1]	others[0]	11079	1			T13	27		T19	4		T20	13
auto[0]	auto[1]	others[1]	1846	1			T13	6		T20	1		T21	2
auto[0]	auto[1]	others[2]	1802	1			T13	5		T20	2		T21	1
auto[0]	auto[1]	others[3]	1932	1			T13	3		T20	1		T21	2
auto[0]	auto[1]	interest[1]	1171	1			T13	6		T20	1		T21	1
auto[0]	auto[1]	interest[4]	7334	1			T13	18		T19	4		T20	10
auto[0]	auto[1]	interest[64]	3426	1			T13	5		T20	2		T21	5
auto[1]	auto[0]	others[0]	3743	1			T1	133		T12	5		T13	105
auto[1]	auto[0]	others[1]	596	1			T1	11		T12	1		T13	11
auto[1]	auto[0]	others[2]	624	1			T1	26		T13	17		T20	11
auto[1]	auto[0]	others[3]	664	1			T1	19		T12	1		T13	19
auto[1]	auto[0]	interest[1]	395	1			T1	11		T13	12		T20	6
auto[1]	auto[0]	interest[4]	2455	1			T1	93		T12	3		T13	67
auto[1]	auto[0]	interest[64]	1210	1			T1	46		T12	2		T13	29

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal