Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	569	1			T18	4		T31	17		T32	15
all_values[1]	569	1			T18	4		T31	17		T32	15
all_values[2]	569	1			T18	4		T31	17		T32	15
all_values[3]	569	1			T18	4		T31	17		T32	15
all_values[4]	569	1			T18	4		T31	17		T32	15
all_values[5]	569	1			T18	4		T31	17		T32	15
all_values[6]	569	1			T18	4		T31	17		T32	15
all_values[7]	569	1			T18	4		T31	17		T32	15

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2477

1

T18

20

T31

68

T32

65

auto[1]

2075

1

T18

12

T31

68

T32

55

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1815

1

T18

12

T31

55

T32

52

auto[1]

2737

1

T18

20

T31

81

T32

68

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2553

1

T18

21

T31

77

T32

73

auto[1]

1999

1

T18

11

T31

59

T32

47

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	126	1			T18	1		T31	1		T32	4
all_values[0]	auto[0]	auto[0]	auto[1]	46	1			T31	1		T32	1		T38	3
all_values[0]	auto[0]	auto[1]	auto[0]	97	1			T31	5		T32	5		T38	6
all_values[0]	auto[0]	auto[1]	auto[1]	48	1			T18	1		T31	2		T38	2
all_values[0]	auto[1]	auto[0]	auto[1]	129	1			T31	1		T32	3		T38	8
all_values[0]	auto[1]	auto[1]	auto[1]	123	1			T18	2		T31	7		T32	2
all_values[1]	auto[0]	auto[0]	auto[0]	121	1			T18	1		T31	3		T32	11
all_values[1]	auto[0]	auto[0]	auto[1]	49	1			T31	2		T38	6		T52	3
all_values[1]	auto[0]	auto[1]	auto[0]	92	1			T31	3		T32	2		T38	11
all_values[1]	auto[0]	auto[1]	auto[1]	54	1			T18	2		T31	2		T38	2
all_values[1]	auto[1]	auto[0]	auto[1]	134	1			T18	1		T31	4		T32	2
all_values[1]	auto[1]	auto[1]	auto[1]	119	1			T31	3		T38	4		T52	5
all_values[2]	auto[0]	auto[0]	auto[0]	114	1			T31	2		T38	7		T52	3
all_values[2]	auto[0]	auto[0]	auto[1]	49	1			T31	1		T32	2		T38	2
all_values[2]	auto[0]	auto[1]	auto[0]	100	1			T31	5		T32	3		T38	4
all_values[2]	auto[0]	auto[1]	auto[1]	49	1			T18	2		T31	1		T32	3
all_values[2]	auto[1]	auto[0]	auto[1]	135	1			T18	1		T31	5		T32	4
all_values[2]	auto[1]	auto[1]	auto[1]	122	1			T18	1		T31	3		T32	3
all_values[3]	auto[0]	auto[0]	auto[0]	136	1			T18	2		T31	4		T32	1
all_values[3]	auto[0]	auto[0]	auto[1]	45	1			T31	1		T32	2		T38	5
all_values[3]	auto[0]	auto[1]	auto[0]	137	1			T18	1		T31	1		T32	6
all_values[3]	auto[0]	auto[1]	auto[1]	42	1			T31	2		T32	2		T38	2
all_values[3]	auto[1]	auto[0]	auto[1]	113	1			T18	1		T31	5		T32	2
all_values[3]	auto[1]	auto[1]	auto[1]	96	1			T31	4		T32	2		T38	7
all_values[4]	auto[0]	auto[0]	auto[0]	95	1			T31	3		T32	2		T38	4
all_values[4]	auto[0]	auto[0]	auto[1]	53	1			T31	1		T32	3		T38	1
all_values[4]	auto[0]	auto[1]	auto[0]	90	1			T31	4		T32	3		T38	12
all_values[4]	auto[0]	auto[1]	auto[1]	64	1			T18	1		T31	1		T32	1
all_values[4]	auto[1]	auto[0]	auto[1]	155	1			T18	3		T31	5		T32	4
all_values[4]	auto[1]	auto[1]	auto[1]	112	1			T31	3		T32	2		T38	8
all_values[5]	auto[0]	auto[0]	auto[0]	171	1			T18	3		T31	7		T32	4
all_values[5]	auto[0]	auto[1]	auto[0]	141	1			T31	3		T32	4		T38	11
all_values[5]	auto[1]	auto[0]	auto[1]	157	1			T18	1		T31	4		T32	4
all_values[5]	auto[1]	auto[1]	auto[1]	100	1			T31	3		T32	3		T38	3
all_values[6]	auto[0]	auto[0]	auto[0]	124	1			T18	3		T31	2		T32	2
all_values[6]	auto[0]	auto[0]	auto[1]	65	1			T31	3		T32	2		T38	4
all_values[6]	auto[0]	auto[1]	auto[0]	79	1			T18	1		T31	2		T38	7
all_values[6]	auto[0]	auto[1]	auto[1]	56	1			T31	4		T32	3		T38	3
all_values[6]	auto[1]	auto[0]	auto[1]	130	1			T31	1		T32	4		T38	7
all_values[6]	auto[1]	auto[1]	auto[1]	115	1			T31	5		T32	4		T38	5
all_values[7]	auto[0]	auto[0]	auto[0]	115	1			T31	9		T32	3		T38	6
all_values[7]	auto[0]	auto[0]	auto[1]	73	1			T18	2		T32	1		T38	3
all_values[7]	auto[0]	auto[1]	auto[0]	77	1			T31	1		T32	2		T38	7
all_values[7]	auto[0]	auto[1]	auto[1]	45	1			T18	1		T31	1		T32	1
all_values[7]	auto[1]	auto[0]	auto[1]	142	1			T18	1		T31	3		T32	4
all_values[7]	auto[1]	auto[1]	auto[1]	117	1			T31	3		T32	4		T38	10

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal