Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	297607	1			T2	1		T3	1		T6	1
all_values[1]	297607	1			T2	1		T3	1		T6	1
all_values[2]	297607	1			T2	1		T3	1		T6	1
all_values[3]	297607	1			T2	1		T3	1		T6	1
all_values[4]	297607	1			T2	1		T3	1		T6	1
all_values[5]	297607	1			T2	1		T3	1		T6	1
all_values[6]	297607	1			T2	1		T3	1		T6	1
all_values[7]	297607	1			T2	1		T3	1		T6	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2378425

1

T2

8

T3

8

T6

8

auto[1]

2431

1

T31

27

T38

63

T39

100

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2378582

1

T2

8

T3

8

T6

8

auto[1]

2274

1

T14

1

T61

5

T17

8

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	297183	1			T2	1		T3	1		T6	1
all_values[0]	auto[0]	auto[1]	123	1			T31	3		T39	3		T40	2
all_values[0]	auto[1]	auto[0]	175	1			T38	6		T39	16		T40	6
all_values[0]	auto[1]	auto[1]	126	1			T31	1		T38	2		T39	1
all_values[1]	auto[0]	auto[0]	297168	1			T2	1		T3	1		T6	1
all_values[1]	auto[0]	auto[1]	132	1			T39	6		T40	2		T160	3
all_values[1]	auto[1]	auto[0]	172	1			T31	1		T38	6		T39	5
all_values[1]	auto[1]	auto[1]	135	1			T31	1		T38	3		T39	6
all_values[2]	auto[0]	auto[0]	297178	1			T2	1		T3	1		T6	1
all_values[2]	auto[0]	auto[1]	144	1			T31	1		T38	1		T39	7
all_values[2]	auto[1]	auto[0]	157	1			T38	2		T39	6		T40	1
all_values[2]	auto[1]	auto[1]	128	1			T38	6		T39	4		T40	3
all_values[3]	auto[0]	auto[0]	297166	1			T2	1		T3	1		T6	1
all_values[3]	auto[0]	auto[1]	122	1			T61	5		T39	4		T40	5
all_values[3]	auto[1]	auto[0]	174	1			T31	5		T38	4		T39	5
all_values[3]	auto[1]	auto[1]	145	1			T38	5		T39	3		T40	3
all_values[4]	auto[0]	auto[0]	297194	1			T2	1		T3	1		T6	1
all_values[4]	auto[0]	auto[1]	137	1			T293	1		T39	2		T40	3
all_values[4]	auto[1]	auto[0]	163	1			T31	4		T38	6		T39	9
all_values[4]	auto[1]	auto[1]	113	1			T38	2		T39	5		T40	4
all_values[5]	auto[0]	auto[0]	296957	1			T2	1		T3	1		T6	1
all_values[5]	auto[0]	auto[1]	354	1			T14	1		T17	8		T52	6
all_values[5]	auto[1]	auto[0]	191	1			T31	4		T38	8		T39	10
all_values[5]	auto[1]	auto[1]	105	1			T31	1		T38	1		T39	3
all_values[6]	auto[0]	auto[0]	297183	1			T2	1		T3	1		T6	1
all_values[6]	auto[0]	auto[1]	118	1			T38	2		T39	6		T40	3
all_values[6]	auto[1]	auto[0]	188	1			T31	5		T38	3		T39	9
all_values[6]	auto[1]	auto[1]	118	1			T38	2		T39	4		T40	1
all_values[7]	auto[0]	auto[0]	297158	1			T2	1		T3	1		T6	1
all_values[7]	auto[0]	auto[1]	108	1			T38	1		T39	4		T40	5
all_values[7]	auto[1]	auto[0]	175	1			T31	3		T38	3		T39	6
all_values[7]	auto[1]	auto[1]	166	1			T31	2		T38	4		T39	8