Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
72.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	32	52	61.90

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	28	20	41.67	100	1	1	0
cr_modeXdummyXnum_lanes	36	4	32	88.89	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1086	1			T2	12		T3	2		T12	8
auto[SpiFlashAddrCfg]	852	1			T2	6		T5	3		T12	8
auto[SpiFlashAddr3b]	919	1			T2	4		T7	3		T12	6
auto[SpiFlashAddr4b]	862	1			T2	6		T11	6		T12	10

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2913

1

T2

28

T3

2

T5

3

auto[1]

806

1

T12

32

T65

16

T66

24

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1950

1

T2

18

T11

4

T12

24

auto[1]

1769

1

T2

10

T3

2

T5

3

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1433	1			T2	14		T3	2		T11	2
values[1]	89	1			T63	4		T69	4		T68	2
values[2]	182	1			T12	4		T124	2		T63	4
values[3]	177	1			T2	2		T11	2		T12	2
values[4]	146	1			T5	3		T58	2		T94	2
values[5]	159	1			T12	4		T58	4		T63	2
values[6]	166	1			T7	3		T62	10		T63	2
values[7]	151	1			T12	4		T58	2		T63	6
values[8]	1216	1			T2	12		T11	2		T12	10

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3140

1

T2

28

T3

2

T11

6

auto[1]

579

1

T5

3

T7

3

T61

15

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3623

1

T2

28

T3

2

T5

3

write

96

1

T62

6

T63

2

T64

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1808

1

T2

10

T5

3

T7

3

valids[0x1]

1911

1

T2

18

T3

2

T11

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	168	1			T2	10		T12	2		T58	2
internal_process_ops[0x5a]	152	1			T12	6		T45	4		T63	4
internal_process_ops[0x05]	158	1			T44	2		T93	2		T94	2
internal_process_ops[0x35]	206	1			T3	2		T44	2		T45	2
internal_process_ops[0x15]	170	1			T2	2		T45	2		T65	2
internal_process_ops[0x03]	220	1			T12	4		T44	2		T65	2
internal_process_ops[0x0b]	226	1			T2	2		T12	4		T45	2
internal_process_ops[0x3b]	284	1			T7	3		T58	2		T61	8
internal_process_ops[0x6b]	249	1			T2	4		T12	2		T61	4
internal_process_ops[0xbb]	266	1			T178	4		T84	6		T175	8
internal_process_ops[0xeb]	292	1			T2	4		T5	3		T58	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3683

1

T2

28

T3

2

T5

3

auto[1]

36

1

T65

2

T66

2

T67

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3719

1

T2

28

T3

2

T5

3

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	28	20	41.67	28
Automatically Generated Cross Bins	48	28	20	41.67	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[write]	*	*	*	--	--	16

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

878

1

T2

12

T3

2

T58

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

188

1

T12

8

T65

2

T66

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

466

1

T2

6

T58

6

T44

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

160

1

T12

8

T65

2

T66

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

492

1

T2

4

T45

8

T62

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

216

1

T12

6

T65

4

T66

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

438

1

T2

6

T11

6

T58

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

206

1

T12

10

T65

6

T66

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12

1

T62

4

T281

2

T219

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

6

1

T65

2

T67

2

T74

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

18

1

T62

2

T64

2

T291

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

10

1

T66

2

T70

2

T71

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

24

1

T178

8

T222

2

T291

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

14

1

T72

4

T73

6

T75

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

6

1

T63

2

T216

2

T280

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

6

1

T76

4

T221

2

-

-

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

2

1

T292

2

-

-

-

-

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

198

1

T5

3

T61

4

T78

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

173

1

T7

3

T61

8

T78

8

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

206

1

T61

3

T78

8

T84

5

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	4	32	88.89	4

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0] , values[1]]	[valids[0x0]]	--	--	2
[auto[1]]	[values[3]]	[valids[0x1]]	0	1	1

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	306	1			T11	2		T12	2		T58	4
auto[0]	values[0]	valids[0x1]	1070	1			T2	14		T3	2		T12	6
auto[0]	values[1]	valids[0x1]	82	1			T63	4		T69	4		T68	2
auto[0]	values[2]	valids[0x0]	100	1			T124	2		T63	4		T25	2
auto[0]	values[2]	valids[0x1]	44	1			T12	4		T65	4		T242	4
auto[0]	values[3]	valids[0x0]	96	1			T2	2		T12	2		T45	4
auto[0]	values[3]	valids[0x1]	46	1			T11	2		T94	2		T25	2
auto[0]	values[4]	valids[0x0]	76	1			T58	2		T94	2		T66	2
auto[0]	values[4]	valids[0x1]	34	1			T226	2		T266	2		T191	2
auto[0]	values[5]	valids[0x0]	48	1			T58	4		T63	2		T64	2
auto[0]	values[5]	valids[0x1]	44	1			T12	4		T239	6		T92	4
auto[0]	values[6]	valids[0x0]	94	1			T62	10		T63	2		T66	4
auto[0]	values[6]	valids[0x1]	36	1			T176	2		T189	4		T91	4
auto[0]	values[7]	valids[0x0]	94	1			T12	4		T58	2		T63	2
auto[0]	values[7]	valids[0x1]	34	1			T63	4		T228	4		T254	4
auto[0]	values[8]	valids[0x0]	608	1			T2	8		T58	4		T45	6
auto[0]	values[8]	valids[0x1]	328	1			T2	4		T11	2		T12	10
auto[1]	values[0]	valids[0x1]	57	1			T84	8		T293	2		T294	3
auto[1]	values[1]	valids[0x1]	7	1			T295	7		-	-		-	-
auto[1]	values[2]	valids[0x0]	22	1			T296	6		T297	4		T295	6
auto[1]	values[2]	valids[0x1]	16	1			T298	6		T299	5		T292	5
auto[1]	values[3]	valids[0x0]	35	1			T61	4		T300	2		T301	8
auto[1]	values[4]	valids[0x0]	26	1			T5	3		T302	3		T299	2
auto[1]	values[4]	valids[0x1]	10	1			T303	8		T292	2		-	-
auto[1]	values[5]	valids[0x0]	42	1			T293	4		T304	7		T305	15
auto[1]	values[5]	valids[0x1]	25	1			T306	4		T307	8		T305	8
auto[1]	values[6]	valids[0x0]	31	1			T7	3		T85	5		T308	10
auto[1]	values[6]	valids[0x1]	5	1			T298	5		-	-		-	-
auto[1]	values[7]	valids[0x0]	19	1			T309	4		T301	4		T294	2
auto[1]	values[7]	valids[0x1]	4	1			T310	4		-	-		-	-
auto[1]	values[8]	valids[0x0]	211	1			T61	11		T78	16		T84	15
auto[1]	values[8]	valids[0x1]	69	1			T78	6		T311	6		T312	4