Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1450039 1 T2 1 T3 1120 T5 35582


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1299265 1 T2 1 T3 96 T5 35582
auto[1] 150774 1 T3 1024 T44 1494 T45 768


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 330705 1 T2 1 T3 30 T5 4201
auto[524288:1048575] 192770 1 T5 936 T7 29 T57 83
auto[1048576:1572863] 151698 1 T3 95 T5 11351 T7 204
auto[1572864:2097151] 173515 1 T7 235 T57 86 T61 190
auto[2097152:2621439] 165263 1 T3 995 T5 5219 T7 170
auto[2621440:3145727] 176072 1 T5 9057 T7 369 T57 2
auto[3145728:3670015] 150060 1 T5 3022 T7 125 T44 68
auto[3670016:4194303] 109956 1 T5 1796 T7 612 T57 94


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 162953 1 T2 1 T3 1028 T5 138
auto[1] 1287086 1 T3 92 T5 35444 T7 2206


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1450039 1 T2 1 T3 1120 T5 35582


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 229085 1 T2 1 T3 30 T5 4201
auto[0] auto[0] auto[0:524287] auto[1] 101620 1 T44 512 T45 376 T25 6056
auto[0] auto[0] auto[524288:1048575] auto[0] 190309 1 T5 936 T7 29 T57 83
auto[0] auto[0] auto[524288:1048575] auto[1] 2461 1 T91 11 T92 34 T173 138
auto[0] auto[0] auto[1048576:1572863] auto[0] 142235 1 T3 63 T5 11351 T7 204
auto[0] auto[0] auto[1048576:1572863] auto[1] 9463 1 T3 32 T44 491 T45 254
auto[0] auto[0] auto[1572864:2097151] auto[0] 165917 1 T7 235 T57 86 T61 190
auto[0] auto[0] auto[1572864:2097151] auto[1] 7598 1 T91 228 T118 514 T119 40
auto[0] auto[0] auto[2097152:2621439] auto[0] 160830 1 T3 3 T5 5219 T7 170
auto[0] auto[0] auto[2097152:2621439] auto[1] 4433 1 T3 992 T45 1 T91 42
auto[0] auto[0] auto[2621440:3145727] auto[0] 161801 1 T5 9057 T7 369 T57 2
auto[0] auto[0] auto[2621440:3145727] auto[1] 14271 1 T44 491 T118 768 T173 4356
auto[0] auto[0] auto[3145728:3670015] auto[0] 147594 1 T5 3022 T7 125 T44 68
auto[0] auto[0] auto[3145728:3670015] auto[1] 2466 1 T118 269 T119 10 T174 2
auto[0] auto[0] auto[3670016:4194303] auto[0] 101494 1 T5 1796 T7 612 T57 94
auto[0] auto[0] auto[3670016:4194303] auto[1] 8462 1 T45 137 T119 245 T174 255


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 162953 1 T2 1 T3 1028 T5 138
auto[0] auto[0] auto[1] 1287086 1 T3 92 T5 35444 T7 2206

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