Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.34	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	36	92	71.88

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	36	92	71.88	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2334

1

T2

28

T3

2

T11

6

auto[1]

806

1

T12

32

T65

16

T66

24

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	366	1			T44	6		T62	22		T66	24
values[1]	374	1			T77	4		T79	4		T68	32
values[2]	326	1			T22	8		T65	16		T178	24
values[3]	250	1			T11	6		T93	12		T25	28
values[4]	480	1			T2	28		T12	32		T46	4
values[5]	510	1			T3	2		T95	2		T63	30
values[6]	364	1			T58	22		T94	20		T23	4
values[7]	470	1			T45	20		T124	2		T64	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	274	1			T45	20		T47	10		T48	14
values[1]	348	1			T11	6		T257	2		T117	8
values[2]	532	1			T2	28		T3	2		T12	32
values[3]	454	1			T63	30		T64	8		T46	4
values[4]	536	1			T58	22		T22	8		T95	2
values[5]	324	1			T94	20		T79	4		T249	4
values[6]	378	1			T44	6		T124	2		T25	28
values[7]	294	1			T65	16		T86	8		T26	2

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	36	92	71.88	36

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[5]]	0	1	1
[auto[0]]	[values[1]]	[values[0]]	0	1	1
[auto[0]]	[values[1]]	[values[7]]	0	1	1
[auto[0]]	[values[2]]	[values[2]]	0	1	1
[auto[0]]	[values[3]]	[values[5]]	0	1	1
[auto[1]]	[values[0]]	[values[1] , values[2] , values[3]]	--	--	3
[auto[1]]	[values[0]]	[values[6]]	0	1	1
[auto[1]]	[values[1]]	[values[1]]	0	1	1
[auto[1]]	[values[1]]	[values[4]]	0	1	1
[auto[1]]	[values[1]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[2]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[2]]	[values[5]]	0	1	1
[auto[1]]	[values[3]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[3]]	[values[3]]	0	1	1
[auto[1]]	[values[3]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[5]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[5]]	[values[5]]	0	1	1
[auto[1]]	[values[5]]	[values[7]]	0	1	1
[auto[1]]	[values[6]]	[values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	6
[auto[1]]	[values[7]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[7]]	[values[5]]	0	1	1

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	70	1			T47	10		T283	18		T92	10
auto[0]	values[0]	values[1]	34	1			T224	14		T313	20		-	-
auto[0]	values[0]	values[2]	54	1			T62	22		T96	14		T118	18
auto[0]	values[0]	values[3]	8	1			T97	8		-	-		-	-
auto[0]	values[0]	values[4]	20	1			T314	20		-	-		-	-
auto[0]	values[0]	values[6]	32	1			T44	6		T287	4		T284	22
auto[0]	values[0]	values[7]	38	1			T250	26		T315	12		-	-
auto[0]	values[1]	values[1]	58	1			T119	16		T185	8		T217	10
auto[0]	values[1]	values[2]	56	1			T77	4		T316	6		T317	10
auto[0]	values[1]	values[3]	42	1			T267	4		T112	14		T255	4
auto[0]	values[1]	values[4]	62	1			T227	22		T269	32		T318	8
auto[0]	values[1]	values[5]	22	1			T79	4		T274	6		T184	12
auto[0]	values[1]	values[6]	14	1			T319	14		-	-		-	-
auto[0]	values[2]	values[0]	24	1			T48	14		T260	4		T320	6
auto[0]	values[2]	values[1]	40	1			T231	8		T239	32		-	-
auto[0]	values[2]	values[3]	82	1			T178	24		T246	2		T271	10
auto[0]	values[2]	values[4]	36	1			T22	8		T253	6		T321	22
auto[0]	values[2]	values[5]	44	1			T275	6		T219	30		T238	8
auto[0]	values[2]	values[6]	24	1			T24	24		-	-		-	-
auto[0]	values[2]	values[7]	22	1			T211	16		T322	6		-	-
auto[0]	values[3]	values[0]	2	1			T323	2		-	-		-	-
auto[0]	values[3]	values[1]	56	1			T11	6		T257	2		T199	4
auto[0]	values[3]	values[2]	12	1			T93	12		-	-		-	-
auto[0]	values[3]	values[3]	44	1			T176	16		T324	6		T214	18
auto[0]	values[3]	values[4]	16	1			T230	12		T273	4		-	-
auto[0]	values[3]	values[6]	52	1			T25	28		T266	18		T201	4
auto[0]	values[3]	values[7]	8	1			T174	2		T262	6		-	-
auto[0]	values[4]	values[0]	20	1			T244	20		-	-		-	-
auto[0]	values[4]	values[1]	24	1			T226	14		T325	10		-	-
auto[0]	values[4]	values[2]	96	1			T2	28		T326	40		T327	8
auto[0]	values[4]	values[3]	42	1			T46	4		T183	2		T328	12
auto[0]	values[4]	values[4]	40	1			T329	6		T330	34		-	-
auto[0]	values[4]	values[5]	34	1			T195	24		T265	10		-	-
auto[0]	values[4]	values[6]	58	1			T228	16		T291	36		T216	2
auto[0]	values[4]	values[7]	2	1			T90	2		-	-		-	-
auto[0]	values[5]	values[0]	2	1			T331	2		-	-		-	-
auto[0]	values[5]	values[1]	54	1			T117	8		T235	20		T218	26
auto[0]	values[5]	values[2]	90	1			T3	2		T202	20		T81	16
auto[0]	values[5]	values[3]	44	1			T63	30		T268	4		T207	10
auto[0]	values[5]	values[4]	50	1			T95	2		T247	2		T198	14
auto[0]	values[5]	values[5]	26	1			T249	4		T188	22		-	-
auto[0]	values[5]	values[6]	24	1			T187	24		-	-		-	-
auto[0]	values[5]	values[7]	72	1			T242	36		T251	20		T233	16
auto[0]	values[6]	values[0]	16	1			T261	16		-	-		-	-
auto[0]	values[6]	values[1]	4	1			T197	2		T332	2		-	-
auto[0]	values[6]	values[2]	30	1			T240	10		T252	20		-	-
auto[0]	values[6]	values[3]	22	1			T23	4		T272	18		-	-
auto[0]	values[6]	values[4]	70	1			T58	22		T177	2		T180	4
auto[0]	values[6]	values[5]	106	1			T94	20		T333	12		T208	16
auto[0]	values[6]	values[6]	48	1			T223	30		T220	8		T270	10
auto[0]	values[6]	values[7]	28	1			T26	2		T173	26		-	-
auto[0]	values[7]	values[0]	22	1			T45	20		T248	2		-	-
auto[0]	values[7]	values[1]	14	1			T245	14		-	-		-	-
auto[0]	values[7]	values[2]	42	1			T334	12		T200	14		T335	16
auto[0]	values[7]	values[3]	68	1			T64	8		T91	16		T281	22
auto[0]	values[7]	values[4]	80	1			T113	2		T258	26		T212	28
auto[0]	values[7]	values[5]	20	1			T175	20		-	-		-	-
auto[0]	values[7]	values[6]	60	1			T124	2		T222	10		T120	14
auto[0]	values[7]	values[7]	54	1			T86	8		T189	40		T203	6
auto[1]	values[0]	values[0]	34	1			T73	18		T336	16		-	-
auto[1]	values[0]	values[4]	44	1			T66	24		T337	20		-	-
auto[1]	values[0]	values[5]	28	1			T338	28		-	-		-	-
auto[1]	values[0]	values[7]	4	1			T288	4		-	-		-	-
auto[1]	values[1]	values[0]	26	1			T67	22		T237	4		-	-
auto[1]	values[1]	values[2]	56	1			T68	32		T72	24		-	-
auto[1]	values[1]	values[3]	28	1			T191	14		T339	14		-	-
auto[1]	values[1]	values[5]	10	1			T75	10		-	-		-	-
auto[1]	values[2]	values[4]	16	1			T76	16		-	-		-	-
auto[1]	values[2]	values[6]	2	1			T259	2		-	-		-	-
auto[1]	values[2]	values[7]	36	1			T65	16		T340	20		-	-
auto[1]	values[3]	values[2]	14	1			T279	14		-	-		-	-
auto[1]	values[3]	values[4]	36	1			T263	26		T341	10		-	-
auto[1]	values[3]	values[5]	10	1			T204	10		-	-		-	-
auto[1]	values[4]	values[0]	30	1			T70	14		T213	16		-	-
auto[1]	values[4]	values[1]	34	1			T210	24		T342	10		-	-
auto[1]	values[4]	values[2]	32	1			T12	32		-	-		-	-
auto[1]	values[4]	values[3]	8	1			T343	8		-	-		-	-
auto[1]	values[4]	values[4]	22	1			T225	22		-	-		-	-
auto[1]	values[4]	values[5]	24	1			T190	24		-	-		-	-
auto[1]	values[4]	values[6]	8	1			T243	8		-	-		-	-
auto[1]	values[4]	values[7]	6	1			T344	6		-	-		-	-
auto[1]	values[5]	values[0]	18	1			T254	18		-	-		-	-
auto[1]	values[5]	values[3]	60	1			T264	30		T179	16		T345	14
auto[1]	values[5]	values[4]	16	1			T69	16		-	-		-	-
auto[1]	values[5]	values[6]	54	1			T229	32		T194	10		T346	12
auto[1]	values[6]	values[0]	10	1			T192	10		-	-		-	-
auto[1]	values[6]	values[1]	30	1			T193	4		T196	20		T289	6
auto[1]	values[7]	values[2]	50	1			T74	20		T221	18		T285	12
auto[1]	values[7]	values[3]	6	1			T282	6		-	-		-	-
auto[1]	values[7]	values[4]	28	1			T286	28		-	-		-	-
auto[1]	values[7]	values[6]	2	1			T71	2		-	-		-	-
auto[1]	values[7]	values[7]	24	1			T290	24		-	-		-	-