Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.52	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	4	56	93.33

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	4	56	93.33	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	98	1			T44	2		T95	2		T230	2
auto[ReadAddrCrossIntoMailbox]	28	1			T240	2		T227	8		T203	2
auto[ReadAddrCrossOutOfMailbox]	30	1			T249	2		T220	2		T227	4
auto[ReadAddrCrossAllMailbox]	28	1			T240	2		T227	2		T203	2
auto[ReadAddrOutsideMailbox]	762	1			T2	10		T12	10		T58	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

473

1

T2

5

T12

5

T58

2

auto[1]

473

1

T2

5

T12

5

T58

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	132	1			T12	4		T44	2		T65	2
read_ops[0x0b]	120	1			T2	2		T12	4		T45	2
read_ops[0x3b]	176	1			T58	2		T45	4		T63	2
read_ops[0x6b]	128	1			T2	4		T12	2		T124	2
read_ops[0xbb]	180	1			T178	4		T175	8		T189	6
read_ops[0xeb]	210	1			T2	4		T58	2		T45	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	4	56	93.33	4

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x0b]]	[auto[ReadAddrCrossIntoMailbox]]	*	--	--	2
[read_ops[0x6b]]	[auto[ReadAddrCrossIntoMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	10	1			T44	1		T240	1		T277	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	10	1			T44	1		T240	1		T277	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	6	1			T240	1		T227	3		T250	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	6	1			T240	1		T227	3		T250	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T227	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T227	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T240	1		T227	1		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T240	1		T227	1		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	47	1			T12	2		T65	1		T25	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	47	1			T12	2		T65	1		T25	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T95	1		T117	1		T226	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T95	1		T117	1		T226	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T315	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T315	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T215	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	1	1			T215	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	50	1			T2	1		T12	2		T45	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	50	1			T2	1		T12	2		T45	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T230	1		T226	1		T197	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T230	1		T226	1		T197	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T252	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T252	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T249	1		T220	1		T252	3
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T249	1		T220	1		T252	3
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T316	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	1	1			T316	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	73	1			T58	1		T45	2		T63	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	73	1			T58	1		T45	2		T63	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	4	1			T117	1		T240	1		T347	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	4	1			T117	1		T240	1		T347	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T268	1		T315	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T268	1		T315	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T252	1		T347	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T252	1		T347	1		-	-
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	56	1			T2	2		T12	1		T124	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	56	1			T2	2		T12	1		T124	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	12	1			T268	1		T325	1		T182	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	12	1			T268	1		T325	1		T182	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T203	1		T215	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T203	1		T215	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T277	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T277	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T250	1		T215	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T250	1		T215	1		-	-
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	73	1			T178	2		T175	4		T189	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	73	1			T178	2		T175	4		T189	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T226	2		T324	2		T318	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T226	2		T324	2		T318	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	5	1			T227	1		T348	1		T215	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	5	1			T227	1		T348	1		T215	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T227	1		T203	1		T241	3
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T227	1		T203	1		T241	3
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	6	1			T203	1		T250	2		T322	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	6	1			T203	1		T250	2		T322	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	82	1			T2	2		T58	1		T45	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	82	1			T2	2		T58	1		T45	3