Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	297607	1			T2	1		T3	1		T6	1
all_pins[1]	297607	1			T2	1		T3	1		T6	1
all_pins[2]	297607	1			T2	1		T3	1		T6	1
all_pins[3]	297607	1			T2	1		T3	1		T6	1
all_pins[4]	297607	1			T2	1		T3	1		T6	1
all_pins[5]	297607	1			T2	1		T3	1		T6	1
all_pins[6]	297607	1			T2	1		T3	1		T6	1
all_pins[7]	297607	1			T2	1		T3	1		T6	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2379820	1			T2	8		T3	8		T6	8
values[0x1]	1036	1			T31	5		T38	25		T39	34
transitions[0x0=>0x1]	721	1			T31	5		T38	12		T39	29
transitions[0x1=>0x0]	736	1			T31	5		T38	12		T39	29

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	297481	1			T2	1		T3	1		T6	1
all_pins[0]	values[0x1]	126	1			T31	1		T38	2		T39	1
all_pins[0]	transitions[0x0=>0x1]	85	1			T31	1		T38	2		T39	1
all_pins[0]	transitions[0x1=>0x0]	94	1			T31	1		T38	3		T39	6
all_pins[1]	values[0x0]	297472	1			T2	1		T3	1		T6	1
all_pins[1]	values[0x1]	135	1			T31	1		T38	3		T39	6
all_pins[1]	transitions[0x0=>0x1]	98	1			T31	1		T39	6		T40	2
all_pins[1]	transitions[0x1=>0x0]	91	1			T38	3		T39	4		T40	2
all_pins[2]	values[0x0]	297479	1			T2	1		T3	1		T6	1
all_pins[2]	values[0x1]	128	1			T38	6		T39	4		T40	3
all_pins[2]	transitions[0x0=>0x1]	83	1			T38	2		T39	4		T40	2
all_pins[2]	transitions[0x1=>0x0]	100	1			T38	1		T39	3		T40	2
all_pins[3]	values[0x0]	297462	1			T2	1		T3	1		T6	1
all_pins[3]	values[0x1]	145	1			T38	5		T39	3		T40	3
all_pins[3]	transitions[0x0=>0x1]	103	1			T38	3		T39	1		T160	6
all_pins[3]	transitions[0x1=>0x0]	71	1			T39	3		T40	1		T363	6
all_pins[4]	values[0x0]	297494	1			T2	1		T3	1		T6	1
all_pins[4]	values[0x1]	113	1			T38	2		T39	5		T40	4
all_pins[4]	transitions[0x0=>0x1]	89	1			T38	1		T39	5		T40	3
all_pins[4]	transitions[0x1=>0x0]	81	1			T31	1		T39	3		T40	1
all_pins[5]	values[0x0]	297502	1			T2	1		T3	1		T6	1
all_pins[5]	values[0x1]	105	1			T31	1		T38	1		T39	3
all_pins[5]	transitions[0x0=>0x1]	78	1			T31	1		T38	1		T39	3
all_pins[5]	transitions[0x1=>0x0]	91	1			T38	2		T39	4		T40	1
all_pins[6]	values[0x0]	297489	1			T2	1		T3	1		T6	1
all_pins[6]	values[0x1]	118	1			T38	2		T39	4		T40	1
all_pins[6]	transitions[0x0=>0x1]	71	1			T39	2		T160	3		T363	1
all_pins[6]	transitions[0x1=>0x0]	119	1			T31	2		T38	2		T39	6
all_pins[7]	values[0x0]	297441	1			T2	1		T3	1		T6	1
all_pins[7]	values[0x1]	166	1			T31	2		T38	4		T39	8
all_pins[7]	transitions[0x0=>0x1]	114	1			T31	2		T38	3		T39	7
all_pins[7]	transitions[0x1=>0x0]	89	1			T31	1		T38	1		T40	2