Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
63.01	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	54	74	57.81

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	54	74	57.81	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	336	1			T2	28		T11	6		T48	14
values[1]	394	1			T45	20		T26	2		T175	20
values[2]	440	1			T58	22		T63	30		T79	4
values[3]	454	1			T95	2		T65	16		T77	4
values[4]	292	1			T3	2		T46	4		T25	28
values[5]	450	1			T44	6		T64	8		T94	20
values[6]	532	1			T12	32		T124	2		T62	22
values[7]	242	1			T22	8		T47	10		T176	16

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	438	1			T124	2		T64	8		T77	4
values[1]	374	1			T23	4		T177	2		T66	24
values[2]	326	1			T22	8		T63	30		T48	14
values[3]	364	1			T2	28		T3	2		T44	6
values[4]	480	1			T12	32		T58	22		T94	20
values[5]	506	1			T62	22		T95	2		T90	2
values[6]	308	1			T11	6		T25	28		T24	24
values[7]	344	1			T45	20		T65	16		T178	24

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3104

1

T2

28

T3

2

T11

6

auto[1]

36

1

T65

2

T66

2

T67

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	54	74	57.81	54

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	8
[auto[1]]	[values[2]]	*	--	--	8
[auto[1]]	[values[7]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[7]]	0	1	1
[auto[0]]	[values[1]]	[values[3]]	0	1	1
[auto[1]]	[values[1]]	[values[0]]	0	1	1
[auto[1]]	[values[1]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[1]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[3]]	[values[0]]	0	1	1
[auto[1]]	[values[3]]	[values[3] , values[4] , values[5] , values[6]]	--	--	4
[auto[1]]	[values[4]]	[values[1] , values[2] , values[3] , values[4]]	--	--	4
[auto[1]]	[values[4]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[5]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[5]]	[values[4]]	0	1	1
[auto[1]]	[values[5]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[6]]	[values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	5

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	16	1			T179	16		-	-		-	-
auto[0]	values[0]	values[1]	24	1			T180	4		T181	10		T182	4
auto[0]	values[0]	values[2]	74	1			T48	14		T183	2		T184	12
auto[0]	values[0]	values[3]	68	1			T2	28		T174	2		T185	8
auto[0]	values[0]	values[4]	60	1			T186	14		T187	24		T188	22
auto[0]	values[0]	values[5]	64	1			T189	40		T190	24		-	-
auto[0]	values[0]	values[6]	30	1			T11	6		T191	14		T192	10
auto[0]	values[1]	values[0]	140	1			T193	4		T194	10		T195	24
auto[0]	values[1]	values[1]	40	1			T96	14		T75	8		T82	18
auto[0]	values[1]	values[2]	36	1			T119	16		T196	20		-	-
auto[0]	values[1]	values[4]	36	1			T67	20		T81	16		-	-
auto[0]	values[1]	values[5]	48	1			T175	20		T197	2		T198	14
auto[0]	values[1]	values[6]	68	1			T199	4		T200	14		T201	4
auto[0]	values[1]	values[7]	22	1			T45	20		T26	2		-	-
auto[0]	values[2]	values[0]	98	1			T202	20		T173	26		T120	14
auto[0]	values[2]	values[1]	20	1			T23	4		T203	6		T204	10
auto[0]	values[2]	values[2]	52	1			T63	30		T205	18		T206	4
auto[0]	values[2]	values[3]	30	1			T79	4		T207	10		T208	16
auto[0]	values[2]	values[4]	78	1			T58	22		T209	12		T210	24
auto[0]	values[2]	values[5]	100	1			T211	16		T212	28		T213	16
auto[0]	values[2]	values[6]	42	1			T24	24		T214	18		-	-
auto[0]	values[2]	values[7]	20	1			T215	20		-	-		-	-
auto[0]	values[3]	values[0]	16	1			T77	4		T216	2		T217	10
auto[0]	values[3]	values[1]	90	1			T72	18		T218	26		T219	30
auto[0]	values[3]	values[2]	58	1			T220	8		T73	12		T221	16
auto[0]	values[3]	values[3]	10	1			T222	10		-	-		-	-
auto[0]	values[3]	values[4]	90	1			T223	30		T224	14		T225	22
auto[0]	values[3]	values[5]	62	1			T95	2		T226	14		T97	8
auto[0]	values[3]	values[6]	36	1			T112	14		T227	22		-	-
auto[0]	values[3]	values[7]	76	1			T65	14		T228	16		T229	32
auto[0]	values[4]	values[0]	50	1			T230	12		T231	8		T232	12
auto[0]	values[4]	values[1]	18	1			T177	2		T233	16		-	-
auto[0]	values[4]	values[2]	2	1			T234	2		-	-		-	-
auto[0]	values[4]	values[3]	92	1			T3	2		T235	20		T236	18
auto[0]	values[4]	values[4]	16	1			T46	4		T237	4		T238	8
auto[0]	values[4]	values[5]	56	1			T90	2		T239	32		T240	10
auto[0]	values[4]	values[6]	28	1			T25	28		-	-		-	-
auto[0]	values[4]	values[7]	26	1			T91	16		T241	10		-	-
auto[0]	values[5]	values[0]	74	1			T64	8		T69	16		T242	36
auto[0]	values[5]	values[1]	72	1			T243	8		T244	20		T245	14
auto[0]	values[5]	values[2]	30	1			T246	2		T247	2		T248	2
auto[0]	values[5]	values[3]	76	1			T44	6		T86	8		T249	4
auto[0]	values[5]	values[4]	64	1			T94	20		T92	10		T250	26
auto[0]	values[5]	values[5]	62	1			T117	8		T251	20		T252	20
auto[0]	values[5]	values[6]	6	1			T253	6		-	-		-	-
auto[0]	values[5]	values[7]	60	1			T254	18		T255	4		T256	10
auto[0]	values[6]	values[0]	36	1			T124	2		T257	2		T258	26
auto[0]	values[6]	values[1]	56	1			T66	22		T68	32		T259	2
auto[0]	values[6]	values[2]	36	1			T260	4		T261	16		T262	6
auto[0]	values[6]	values[3]	56	1			T93	12		T118	18		T263	26
auto[0]	values[6]	values[4]	90	1			T12	32		T264	30		T265	10
auto[0]	values[6]	values[5]	56	1			T62	22		T266	18		T267	4
auto[0]	values[6]	values[6]	96	1			T268	4		T269	32		T270	10
auto[0]	values[6]	values[7]	100	1			T178	24		T271	10		T272	18
auto[0]	values[7]	values[0]	4	1			T273	4		-	-		-	-
auto[0]	values[7]	values[1]	44	1			T274	6		T275	6		T276	12
auto[0]	values[7]	values[2]	30	1			T22	8		T277	4		T278	18
auto[0]	values[7]	values[3]	30	1			T47	10		T279	14		T280	6
auto[0]	values[7]	values[4]	44	1			T176	16		T281	22		T282	6
auto[0]	values[7]	values[5]	52	1			T283	18		T284	22		T285	12
auto[0]	values[7]	values[6]	2	1			T113	2		-	-		-	-
auto[0]	values[7]	values[7]	36	1			T286	28		T287	4		T288	4
auto[1]	values[1]	values[1]	2	1			T75	2		-	-		-	-
auto[1]	values[1]	values[4]	2	1			T67	2		-	-		-	-
auto[1]	values[3]	values[1]	6	1			T72	6		-	-		-	-
auto[1]	values[3]	values[2]	8	1			T73	6		T221	2		-	-
auto[1]	values[3]	values[7]	2	1			T65	2		-	-		-	-
auto[1]	values[4]	values[0]	2	1			T74	2		-	-		-	-
auto[1]	values[4]	values[5]	2	1			T70	2		-	-		-	-
auto[1]	values[5]	values[3]	2	1			T289	2		-	-		-	-
auto[1]	values[5]	values[5]	4	1			T76	4		-	-		-	-
auto[1]	values[6]	values[0]	2	1			T71	2		-	-		-	-
auto[1]	values[6]	values[1]	2	1			T66	2		-	-		-	-
auto[1]	values[6]	values[7]	2	1			T290	2		-	-		-	-