Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1413

1

T6

22

T13

3

T15

16

auto[1]

1433

1

T6

11

T13

4

T15

15

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

709

1

T15

31

T18

5

T53

4

auto[1]

2137

1

T6

33

T13

7

T20

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2586

1

T6

33

T13

7

T15

15

auto[1]

260

1

T15

16

T18

3

T53

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	539	1			T6	6		T13	1		T15	9
valid[1]	564	1			T6	10		T15	4		T18	2
valid[2]	581	1			T6	6		T13	2		T15	5
valid[3]	565	1			T6	4		T13	1		T15	7
valid[4]	597	1			T6	7		T13	3		T15	6

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	42	1			T15	1		T55	1		T56	3
auto[0]	auto[0]	valid[0]	auto[1]	204	1			T6	2		T13	1		T104	5
auto[0]	auto[0]	valid[1]	auto[0]	43	1			T15	1		T55	3		T56	3
auto[0]	auto[0]	valid[1]	auto[1]	216	1			T6	9		T20	1		T104	3
auto[0]	auto[0]	valid[2]	auto[0]	47	1			T15	2		T55	2		T56	3
auto[0]	auto[0]	valid[2]	auto[1]	207	1			T6	3		T13	2		T20	1
auto[0]	auto[0]	valid[3]	auto[0]	46	1			T15	2		T54	2		T55	4
auto[0]	auto[0]	valid[3]	auto[1]	205	1			T6	2		T104	3		T59	2
auto[0]	auto[0]	valid[4]	auto[0]	43	1			T55	2		T59	1		T103	1
auto[0]	auto[0]	valid[4]	auto[1]	213	1			T6	6		T104	2		T59	1
auto[0]	auto[1]	valid[0]	auto[0]	45	1			T15	3		T53	1		T54	1
auto[0]	auto[1]	valid[0]	auto[1]	204	1			T6	4		T54	2		T104	5
auto[0]	auto[1]	valid[1]	auto[0]	41	1			T15	2		T18	1		T55	3
auto[0]	auto[1]	valid[1]	auto[1]	208	1			T6	1		T20	1		T54	1
auto[0]	auto[1]	valid[2]	auto[0]	48	1			T54	2		T55	1		T59	1
auto[0]	auto[1]	valid[2]	auto[1]	220	1			T6	3		T20	1		T104	4
auto[0]	auto[1]	valid[3]	auto[0]	37	1			T15	1		T18	1		T53	1
auto[0]	auto[1]	valid[3]	auto[1]	225	1			T6	2		T13	1		T54	1
auto[0]	auto[1]	valid[4]	auto[0]	57	1			T15	3		T54	1		T55	2
auto[0]	auto[1]	valid[4]	auto[1]	235	1			T6	1		T13	3		T104	2
auto[1]	auto[0]	valid[0]	auto[0]	25	1			T15	4		T54	2		T56	1
auto[1]	auto[0]	valid[1]	auto[0]	32	1			T15	1		T18	1		T53	1
auto[1]	auto[0]	valid[2]	auto[0]	36	1			T15	2		T54	3		T56	2
auto[1]	auto[0]	valid[3]	auto[0]	26	1			T15	2		T54	1		T56	1
auto[1]	auto[0]	valid[4]	auto[0]	28	1			T15	1		T54	1		T55	1
auto[1]	auto[1]	valid[0]	auto[0]	19	1			T15	1		T18	1		T56	2
auto[1]	auto[1]	valid[1]	auto[0]	24	1			T53	1		T54	1		T55	4
auto[1]	auto[1]	valid[2]	auto[0]	23	1			T15	1		T55	1		T59	2
auto[1]	auto[1]	valid[3]	auto[0]	26	1			T15	2		T56	2		T59	3
auto[1]	auto[1]	valid[4]	auto[0]	21	1			T15	2		T18	1		T55	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal