Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17762

1

T14

2

T15

563

T17

19

auto[1]

21128

1

T6

377

T13

7

T20

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32344

1

T6

377

T13

7

T15

363

auto[1]

6546

1

T14

2

T15

200

T17

11

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	20217	1			T6	206		T13	7		T15	293
others[1]	3177	1			T6	38		T15	52		T17	3
others[2]	3311	1			T6	29		T15	51		T18	21
others[3]	3653	1			T6	24		T14	1		T15	40
interest[1]	2071	1			T6	26		T14	1		T15	27
interest[4]	13329	1			T6	143		T13	7		T15	174
interest[64]	6461	1			T6	54		T15	100		T17	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5661	1			T15	182		T17	3		T18	63
auto[0]	auto[0]	others[1]	938	1			T15	30		T17	2		T18	8
auto[0]	auto[0]	others[2]	986	1			T15	41		T18	12		T53	4
auto[0]	auto[0]	others[3]	1074	1			T15	26		T17	1		T18	9
auto[0]	auto[0]	interest[1]	642	1			T15	19		T18	11		T52	1
auto[0]	auto[0]	interest[4]	3672	1			T15	103		T17	3		T18	39
auto[0]	auto[0]	interest[64]	1915	1			T15	65		T17	2		T18	24
auto[0]	auto[1]	others[0]	11139	1			T6	206		T13	7		T20	4
auto[0]	auto[1]	others[1]	1701	1			T6	38		T54	4		T104	33
auto[0]	auto[1]	others[2]	1800	1			T6	29		T54	5		T104	38
auto[0]	auto[1]	others[3]	1936	1			T6	24		T54	6		T104	31
auto[0]	auto[1]	interest[1]	1081	1			T6	26		T54	2		T104	13
auto[0]	auto[1]	interest[4]	7464	1			T6	143		T13	7		T20	4
auto[0]	auto[1]	interest[64]	3471	1			T6	54		T54	13		T104	62
auto[1]	auto[0]	others[0]	3417	1			T15	111		T17	5		T18	35
auto[1]	auto[0]	others[1]	538	1			T15	22		T17	1		T18	7
auto[1]	auto[0]	others[2]	525	1			T15	10		T18	9		T52	1
auto[1]	auto[0]	others[3]	643	1			T14	1		T15	14		T17	1
auto[1]	auto[0]	interest[1]	348	1			T14	1		T15	8		T17	1
auto[1]	auto[0]	interest[4]	2193	1			T15	71		T17	4		T18	24
auto[1]	auto[0]	interest[64]	1075	1			T15	35		T17	3		T18	7

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal