Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	520	1			T31	4		T38	8		T39	18
all_values[1]	520	1			T31	4		T38	8		T39	18
all_values[2]	520	1			T31	4		T38	8		T39	18
all_values[3]	520	1			T31	4		T38	8		T39	18
all_values[4]	520	1			T31	4		T38	8		T39	18
all_values[5]	520	1			T31	4		T38	8		T39	18
all_values[6]	520	1			T31	4		T38	8		T39	18
all_values[7]	520	1			T31	4		T38	8		T39	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2208

1

T31

12

T38

30

T39

74

auto[1]

1952

1

T31

20

T38

34

T39

70

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1595

1

T31

17

T38

28

T39

54

auto[1]

2565

1

T31

15

T38

36

T39

90

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2354

1

T31

20

T38

40

T39

85

auto[1]

1806

1

T31

12

T38

24

T39

59

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	116	1			T38	2		T39	1		T40	2
all_values[0]	auto[0]	auto[0]	auto[1]	52	1			T31	1		T39	1		T161	2
all_values[0]	auto[0]	auto[1]	auto[0]	81	1			T38	2		T39	8		T40	2
all_values[0]	auto[0]	auto[1]	auto[1]	51	1			T31	1		T38	1		T39	1
all_values[0]	auto[1]	auto[0]	auto[1]	118	1			T31	1		T38	1		T39	6
all_values[0]	auto[1]	auto[1]	auto[1]	102	1			T31	1		T38	2		T39	1
all_values[1]	auto[0]	auto[0]	auto[0]	97	1			T31	1		T38	2		T39	2
all_values[1]	auto[0]	auto[0]	auto[1]	54	1			T39	2		T160	2		T161	4
all_values[1]	auto[0]	auto[1]	auto[0]	92	1			T31	1		T38	3		T39	1
all_values[1]	auto[0]	auto[1]	auto[1]	51	1			T38	1		T39	4		T40	1
all_values[1]	auto[1]	auto[0]	auto[1]	132	1			T31	1		T38	1		T39	5
all_values[1]	auto[1]	auto[1]	auto[1]	94	1			T31	1		T38	1		T39	4
all_values[2]	auto[0]	auto[0]	auto[0]	95	1			T31	2		T38	1		T39	1
all_values[2]	auto[0]	auto[0]	auto[1]	59	1			T38	1		T39	4		T40	1
all_values[2]	auto[0]	auto[1]	auto[0]	79	1			T39	2		T160	1		T161	3
all_values[2]	auto[0]	auto[1]	auto[1]	64	1			T38	2		T39	2		T40	1
all_values[2]	auto[1]	auto[0]	auto[1]	119	1			T31	2		T38	2		T39	7
all_values[2]	auto[1]	auto[1]	auto[1]	104	1			T38	2		T39	2		T40	4
all_values[3]	auto[0]	auto[0]	auto[0]	107	1			T38	1		T39	6		T160	2
all_values[3]	auto[0]	auto[0]	auto[1]	43	1			T39	1		T40	1		T161	1
all_values[3]	auto[0]	auto[1]	auto[0]	75	1			T31	4		T38	1		T39	2
all_values[3]	auto[0]	auto[1]	auto[1]	64	1			T38	2		T39	1		T160	3
all_values[3]	auto[1]	auto[0]	auto[1]	126	1			T38	3		T39	4		T40	5
all_values[3]	auto[1]	auto[1]	auto[1]	105	1			T38	1		T39	4		T40	4
all_values[4]	auto[0]	auto[0]	auto[0]	110	1			T31	1		T38	3		T39	3
all_values[4]	auto[0]	auto[0]	auto[1]	50	1			T40	1		T362	1		T162	4
all_values[4]	auto[0]	auto[1]	auto[0]	80	1			T31	2		T38	1		T39	6
all_values[4]	auto[0]	auto[1]	auto[1]	48	1			T38	1		T39	2		T40	1
all_values[4]	auto[1]	auto[0]	auto[1]	133	1			T31	1		T38	1		T39	4
all_values[4]	auto[1]	auto[1]	auto[1]	99	1			T38	2		T39	3		T40	4
all_values[5]	auto[0]	auto[0]	auto[0]	150	1			T31	1		T38	2		T39	3
all_values[5]	auto[0]	auto[1]	auto[0]	146	1			T31	2		T38	4		T39	8
all_values[5]	auto[1]	auto[0]	auto[1]	122	1			T31	1		T38	1		T39	3
all_values[5]	auto[1]	auto[1]	auto[1]	102	1			T38	1		T39	4		T40	3
all_values[6]	auto[0]	auto[0]	auto[0]	102	1			T38	3		T39	4		T40	4
all_values[6]	auto[0]	auto[0]	auto[1]	51	1			T38	1		T39	3		T40	1
all_values[6]	auto[0]	auto[1]	auto[0]	96	1			T31	2		T38	1		T39	3
all_values[6]	auto[0]	auto[1]	auto[1]	51	1			T38	1		T39	3		T160	2
all_values[6]	auto[1]	auto[0]	auto[1]	122	1			T38	2		T39	5		T40	3
all_values[6]	auto[1]	auto[1]	auto[1]	98	1			T31	2		T40	1		T160	4
all_values[7]	auto[0]	auto[0]	auto[0]	93	1			T38	1		T39	3		T161	4
all_values[7]	auto[0]	auto[0]	auto[1]	40	1			T39	1		T40	1		T161	1
all_values[7]	auto[0]	auto[1]	auto[0]	76	1			T31	1		T38	1		T39	1
all_values[7]	auto[0]	auto[1]	auto[1]	81	1			T31	1		T38	2		T39	6
all_values[7]	auto[1]	auto[0]	auto[1]	117	1			T38	2		T39	5		T40	4
all_values[7]	auto[1]	auto[1]	auto[1]	113	1			T31	2		T38	2		T39	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal