Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	265414	1			T1	1		T2	1		T3	1
all_values[1]	265414	1			T1	1		T2	1		T3	1
all_values[2]	265414	1			T1	1		T2	1		T3	1
all_values[3]	265414	1			T1	1		T2	1		T3	1
all_values[4]	265414	1			T1	1		T2	1		T3	1
all_values[5]	265414	1			T1	1		T2	1		T3	1
all_values[6]	265414	1			T1	1		T2	1		T3	1
all_values[7]	265414	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2121161

1

T1

8

T2

8

T3

8

auto[1]

2151

1

T33

49

T34

109

T35

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2121293

1

T1

8

T2

8

T3

8

auto[1]

2019

1

T18

3

T19

3

T22

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	265031	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	107	1			T33	2		T34	8		T35	1
all_values[0]	auto[1]	auto[0]	175	1			T33	5		T34	7		T35	4
all_values[0]	auto[1]	auto[1]	101	1			T34	5		T35	1		T368	2
all_values[1]	auto[0]	auto[0]	265025	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	135	1			T33	3		T34	7		T35	4
all_values[1]	auto[1]	auto[0]	131	1			T33	3		T34	12		T35	1
all_values[1]	auto[1]	auto[1]	123	1			T33	4		T34	8		T368	8
all_values[2]	auto[0]	auto[0]	265041	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	106	1			T34	7		T35	2		T368	4
all_values[2]	auto[1]	auto[0]	169	1			T33	2		T34	13		T35	6
all_values[2]	auto[1]	auto[1]	98	1			T33	4		T34	1		T35	2
all_values[3]	auto[0]	auto[0]	265018	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	111	1			T33	1		T34	2		T35	1
all_values[3]	auto[1]	auto[0]	160	1			T33	4		T34	9		T35	2
all_values[3]	auto[1]	auto[1]	125	1			T33	2		T34	8		T35	4
all_values[4]	auto[0]	auto[0]	265006	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	123	1			T33	4		T34	8		T35	2
all_values[4]	auto[1]	auto[0]	154	1			T33	1		T34	6		T35	3
all_values[4]	auto[1]	auto[1]	131	1			T33	5		T34	5		T35	3
all_values[5]	auto[0]	auto[0]	264873	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	281	1			T18	3		T19	3		T22	5
all_values[5]	auto[1]	auto[0]	155	1			T33	3		T34	6		T35	1
all_values[5]	auto[1]	auto[1]	105	1			T33	2		T34	5		T368	8
all_values[6]	auto[0]	auto[0]	265043	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	124	1			T33	2		T34	8		T35	4
all_values[6]	auto[1]	auto[0]	133	1			T33	5		T34	4		T35	2
all_values[6]	auto[1]	auto[1]	114	1			T33	1		T34	6		T35	4
all_values[7]	auto[0]	auto[0]	265031	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	106	1			T33	3		T34	10		T35	2
all_values[7]	auto[1]	auto[0]	148	1			T33	1		T34	10		T35	1
all_values[7]	auto[1]	auto[1]	129	1			T33	7		T34	4		T35	3