Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.23	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	28	56	66.67

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	25	23	47.92	100	1	1	0
cr_modeXdummyXnum_lanes	36	3	33	91.67	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1174	1			T3	2		T4	4		T5	2
auto[SpiFlashAddrCfg]	813	1			T3	6		T5	6		T8	1
auto[SpiFlashAddr3b]	1007	1			T5	8		T8	9		T10	4
auto[SpiFlashAddr4b]	778	1			T3	6		T4	2		T5	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2966

1

T3

14

T4

6

T5

18

auto[1]

806

1

T9

10

T10

24

T71

8

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2063

1

T3

8

T4

4

T5

6

auto[1]

1709

1

T3

6

T4

2

T5

12

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1539	1			T3	2		T4	4		T5	4
values[1]	107	1			T82	2		T26	4		T73	4
values[2]	158	1			T9	2		T95	2		T82	4
values[3]	202	1			T72	2		T46	2		T186	4
values[4]	183	1			T8	9		T9	2		T10	2
values[5]	124	1			T12	4		T80	2		T188	2
values[6]	152	1			T11	4		T78	2		T96	2
values[7]	157	1			T3	2		T8	2		T26	4
values[8]	1150	1			T3	10		T4	2		T5	14

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3228

1

T3

14

T4

6

T5

18

auto[1]

544

1

T8

21

T11

5

T93

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3638

1

T3

14

T4

6

T5

18

write

134

1

T9

4

T10

4

T72

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1702

1

T3

8

T4

2

T5

8

valids[0x1]

2070

1

T3

6

T4

4

T5

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	212	1			T71	2		T44	8		T72	2
internal_process_ops[0x5a]	168	1			T5	2		T10	2		T98	2
internal_process_ops[0x05]	233	1			T3	2		T4	2		T5	2
internal_process_ops[0x35]	189	1			T12	4		T183	2		T96	2
internal_process_ops[0x15]	149	1			T4	2		T10	4		T12	6
internal_process_ops[0x03]	243	1			T3	4		T8	2		T12	4
internal_process_ops[0x0b]	257	1			T5	6		T9	2		T11	1
internal_process_ops[0x3b]	266	1			T5	2		T8	9		T11	4
internal_process_ops[0x6b]	247	1			T3	2		T72	2		T81	4
internal_process_ops[0xbb]	276	1			T3	6		T5	2		T8	1
internal_process_ops[0xeb]	246	1			T8	9		T10	2		T12	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3702

1

T3

14

T4

6

T5

18

auto[1]

70

1

T9

4

T10

4

T73

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3772

1

T3

14

T4

6

T5

18

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	25	23	47.92	25
Automatically Generated Cross Bins	48	25	23	47.92	25
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[write]	*	*	*	--	--	16

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddrCfg]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

920

1

T3

2

T4

4

T5

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

192

1

T9

2

T10

4

T71

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

478

1

T3

6

T5

6

T12

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

150

1

T9

2

T10

2

T71

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

600

1

T5

8

T72

2

T82

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

184

1

T10

4

T81

4

T73

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

368

1

T3

6

T4

2

T5

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

202

1

T9

2

T10

10

T71

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

30

1

T187

6

T230

6

T256

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

24

1

T10

4

T84

4

T86

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

6

1

T249

2

T211

2

T300

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

10

1

T85

2

T77

2

T87

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

18

1

T74

2

T249

6

T243

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

22

1

T73

2

T83

2

T279

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

10

1

T72

2

T287

2

T243

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

14

1

T9

4

T87

2

T204

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

6

1

T27

6

-

-

-

-

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

2

1

T27

2

-

-

-

-

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

169

1

T8

1

T27

2

T301

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

181

1

T8

9

T11

1

T302

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2

1

T27

2

-

-

-

-

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

180

1

T8

11

T11

4

T93

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

4

1

T27

4

-

-

-

-

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	3	33	91.67	3

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[2]]	[valids[0x1]]	0	1	1

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	296	1			T78	2		T23	6		T26	2
auto[0]	values[0]	valids[0x1]	1162	1			T3	2		T4	4		T5	4
auto[0]	values[1]	valids[0x1]	100	1			T82	2		T26	4		T73	4
auto[0]	values[2]	valids[0x0]	82	1			T95	2		T78	2		T98	4
auto[0]	values[2]	valids[0x1]	46	1			T9	2		T82	4		T80	2
auto[0]	values[3]	valids[0x0]	102	1			T72	2		T46	2		T303	2
auto[0]	values[3]	valids[0x1]	62	1			T186	4		T232	2		T83	10
auto[0]	values[4]	valids[0x0]	84	1			T9	2		T10	2		T82	2
auto[0]	values[4]	valids[0x1]	54	1			T71	4		T78	4		T26	8
auto[0]	values[5]	valids[0x0]	76	1			T80	2		T188	2		T249	4
auto[0]	values[5]	valids[0x1]	32	1			T12	4		T232	2		T304	10
auto[0]	values[6]	valids[0x0]	86	1			T78	2		T96	2		T79	2
auto[0]	values[6]	valids[0x1]	38	1			T73	4		T284	4		T230	2
auto[0]	values[7]	valids[0x0]	68	1			T3	2		T26	4		T73	2
auto[0]	values[7]	valids[0x1]	34	1			T83	4		T248	2		T304	2
auto[0]	values[8]	valids[0x0]	568	1			T3	6		T4	2		T5	8
auto[0]	values[8]	valids[0x1]	338	1			T3	4		T5	6		T10	2
auto[1]	values[0]	valids[0x0]	2	1			T27	2		-	-		-	-
auto[1]	values[0]	valids[0x1]	79	1			T27	6		T305	5		T306	3
auto[1]	values[1]	valids[0x1]	7	1			T119	7		-	-		-	-
auto[1]	values[2]	valids[0x0]	30	1			T305	8		T307	5		T308	2
auto[1]	values[3]	valids[0x0]	30	1			T309	4		T310	6		T311	7
auto[1]	values[3]	valids[0x1]	8	1			T27	3		T312	5		-	-
auto[1]	values[4]	valids[0x0]	43	1			T8	9		T27	1		T309	4
auto[1]	values[4]	valids[0x1]	2	1			T313	2		-	-		-	-
auto[1]	values[5]	valids[0x0]	15	1			T27	1		T58	6		T314	4
auto[1]	values[5]	valids[0x1]	1	1			T27	1		-	-		-	-
auto[1]	values[6]	valids[0x0]	21	1			T11	4		T27	1		T302	3
auto[1]	values[6]	valids[0x1]	7	1			T315	3		T119	4		-	-
auto[1]	values[7]	valids[0x0]	40	1			T316	3		T317	4		T318	7
auto[1]	values[7]	valids[0x1]	15	1			T8	2		T302	6		T319	2
auto[1]	values[8]	valids[0x0]	159	1			T8	10		T93	5		T27	4
auto[1]	values[8]	valids[0x1]	85	1			T11	1		T27	1		T301	3