Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1671000 1 T3 2017 T4 4771 T5 5


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1550249 1 T3 2017 T4 1 T5 1
auto[1] 120751 1 T4 4770 T5 4 T44 8542


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 406103 1 T3 107 T4 4771 T5 5
auto[524288:1048575] 201129 1 T3 86 T8 271 T11 774
auto[1048576:1572863] 181187 1 T3 157 T8 95 T11 3662
auto[1572864:2097151] 186597 1 T3 13 T8 918 T11 2725
auto[2097152:2621439] 168446 1 T3 346 T8 386 T11 196
auto[2621440:3145727] 213543 1 T3 142 T8 68 T11 53
auto[3145728:3670015] 165836 1 T3 930 T8 392 T11 3797
auto[3670016:4194303] 148159 1 T3 236 T8 3 T11 171


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 135797 1 T3 41 T4 4771 T5 5
auto[1] 1535203 1 T3 1976 T7 3 T8 3350


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1671000 1 T3 2017 T4 4771 T5 5


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 308100 1 T3 107 T4 1 T5 1
auto[0] auto[0] auto[0:524287] auto[1] 98003 1 T4 4770 T5 4 T44 5289
auto[0] auto[0] auto[524288:1048575] auto[0] 198622 1 T3 86 T8 271 T11 774
auto[0] auto[0] auto[524288:1048575] auto[1] 2507 1 T44 1298 T183 512 T98 1
auto[0] auto[0] auto[1048576:1572863] auto[0] 177075 1 T3 157 T8 95 T11 3662
auto[0] auto[0] auto[1048576:1572863] auto[1] 4112 1 T183 12 T98 9 T46 2
auto[0] auto[0] auto[1572864:2097151] auto[0] 183886 1 T3 13 T8 918 T11 2725
auto[0] auto[0] auto[1572864:2097151] auto[1] 2711 1 T44 1616 T46 9 T139 518
auto[0] auto[0] auto[2097152:2621439] auto[0] 166549 1 T3 346 T8 386 T11 196
auto[0] auto[0] auto[2097152:2621439] auto[1] 1897 1 T44 3 T46 16 T184 1
auto[0] auto[0] auto[2621440:3145727] auto[0] 212825 1 T3 142 T8 68 T11 53
auto[0] auto[0] auto[2621440:3145727] auto[1] 718 1 T183 1 T46 21 T47 5
auto[0] auto[0] auto[3145728:3670015] auto[0] 161155 1 T3 930 T8 392 T11 3797
auto[0] auto[0] auto[3145728:3670015] auto[1] 4681 1 T44 310 T183 18 T46 373
auto[0] auto[0] auto[3670016:4194303] auto[0] 142037 1 T3 236 T8 3 T11 171
auto[0] auto[0] auto[3670016:4194303] auto[1] 6122 1 T44 26 T98 1024 T139 133


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 135797 1 T3 41 T4 4771 T5 5
auto[0] auto[0] auto[1] 1535203 1 T3 1976 T7 3 T8 3350

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