Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	31	97	75.78

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	31	97	75.78	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2430

1

T3

14

T4

6

T5

18

auto[1]

798

1

T9

10

T10

24

T71

8

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	458	1			T73	32		T186	18		T190	8
values[1]	398	1			T45	8		T95	2		T78	16
values[2]	344	1			T9	10		T10	24		T12	20
values[3]	386	1			T3	14		T5	18		T72	10
values[4]	392	1			T4	6		T23	6		T207	28
values[5]	342	1			T118	10		T220	8		T188	12
values[6]	336	1			T71	8		T44	16		T99	6
values[7]	572	1			T183	4		T46	10		T80	22

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	254	1			T4	6		T9	10		T95	2
values[1]	432	1			T10	24		T78	16		T98	32
values[2]	590	1			T183	4		T82	16		T101	6
values[3]	488	1			T96	12		T46	10		T73	32
values[4]	292	1			T3	14		T12	20		T83	26
values[5]	320	1			T71	8		T184	2		T188	12
values[6]	406	1			T5	18		T44	16		T72	10
values[7]	446	1			T74	12		T80	22		T118	10

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	31	97	75.78	31

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[6]]	0	1	1
[auto[0]]	[values[1]]	[values[4]]	0	1	1
[auto[0]]	[values[4]]	[values[1]]	0	1	1
[auto[0]]	[values[4]]	[values[5]]	0	1	1
[auto[1]]	[values[0]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[1]]	[values[0]]	0	1	1
[auto[1]]	[values[1]]	[values[4] , values[5] , values[6] , values[7]]	--	--	4
[auto[1]]	[values[2]]	[values[3] , values[4] , values[5]]	--	--	3
[auto[1]]	[values[2]]	[values[7]]	0	1	1
[auto[1]]	[values[3]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[3]]	[values[4]]	0	1	1
[auto[1]]	[values[3]]	[values[7]]	0	1	1
[auto[1]]	[values[4]]	[values[0]]	0	1	1
[auto[1]]	[values[4]]	[values[4]]	0	1	1
[auto[1]]	[values[4]]	[values[7]]	0	1	1
[auto[1]]	[values[5]]	[values[0]]	0	1	1
[auto[1]]	[values[5]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[6]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[6]]	[values[3]]	0	1	1
[auto[1]]	[values[7]]	[values[0]]	0	1	1
[auto[1]]	[values[7]]	[values[5] , values[6]]	--	--	2

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	20	1			T320	8		T201	12		-	-
auto[0]	values[0]	values[1]	58	1			T187	36		T225	6		T263	2
auto[0]	values[0]	values[2]	80	1			T139	28		T189	2		T287	4
auto[0]	values[0]	values[3]	76	1			T186	18		T138	20		T102	16
auto[0]	values[0]	values[4]	14	1			T321	8		T322	6		-	-
auto[0]	values[0]	values[5]	66	1			T203	14		T210	18		T234	18
auto[0]	values[0]	values[7]	4	1			T290	4		-	-		-	-
auto[0]	values[1]	values[0]	28	1			T95	2		T227	10		T213	16
auto[0]	values[1]	values[1]	114	1			T78	16		T98	32		T191	14
auto[0]	values[1]	values[2]	8	1			T101	6		T254	2		-	-
auto[0]	values[1]	values[3]	28	1			T206	18		T323	10		-	-
auto[0]	values[1]	values[5]	48	1			T25	4		T240	26		T253	18
auto[0]	values[1]	values[6]	46	1			T45	8		T196	28		T127	4
auto[0]	values[1]	values[7]	58	1			T74	12		T281	14		T289	6
auto[0]	values[2]	values[0]	18	1			T211	18		-	-		-	-
auto[0]	values[2]	values[1]	20	1			T324	2		T215	18		-	-
auto[0]	values[2]	values[2]	74	1			T82	16		T135	22		T272	10
auto[0]	values[2]	values[3]	24	1			T96	12		T325	12		-	-
auto[0]	values[2]	values[4]	26	1			T12	20		T326	4		T327	2
auto[0]	values[2]	values[5]	28	1			T261	10		T328	18		-	-
auto[0]	values[2]	values[6]	18	1			T216	18		-	-		-	-
auto[0]	values[2]	values[7]	8	1			T277	8		-	-		-	-
auto[0]	values[3]	values[0]	24	1			T257	24		-	-		-	-
auto[0]	values[3]	values[1]	2	1			T229	2		-	-		-	-
auto[0]	values[3]	values[2]	18	1			T185	8		T237	4		T329	6
auto[0]	values[3]	values[3]	34	1			T221	4		T246	12		T330	18
auto[0]	values[3]	values[4]	40	1			T3	14		T304	26		-	-
auto[0]	values[3]	values[5]	42	1			T76	20		T331	22		-	-
auto[0]	values[3]	values[6]	52	1			T5	18		T72	10		T192	6
auto[0]	values[3]	values[7]	58	1			T264	2		T243	24		T241	14
auto[0]	values[4]	values[0]	34	1			T4	6		T205	24		T332	4
auto[0]	values[4]	values[2]	50	1			T275	24		T239	24		T333	2
auto[0]	values[4]	values[3]	34	1			T266	12		T265	2		T334	20
auto[0]	values[4]	values[4]	54	1			T194	32		T226	14		T335	8
auto[0]	values[4]	values[6]	68	1			T23	6		T120	10		T195	10
auto[0]	values[4]	values[7]	42	1			T56	6		T238	2		T283	30
auto[0]	values[5]	values[0]	24	1			T90	24		-	-		-	-
auto[0]	values[5]	values[1]	28	1			T252	10		T336	2		T337	16
auto[0]	values[5]	values[2]	24	1			T75	14		T338	10		-	-
auto[0]	values[5]	values[3]	38	1			T220	8		T250	2		T242	8
auto[0]	values[5]	values[4]	66	1			T339	14		T340	26		T341	6
auto[0]	values[5]	values[5]	20	1			T188	12		T342	8		-	-
auto[0]	values[5]	values[6]	28	1			T343	28		-	-		-	-
auto[0]	values[5]	values[7]	44	1			T118	10		T231	18		T126	16
auto[0]	values[6]	values[0]	16	1			T99	6		T218	10		-	-
auto[0]	values[6]	values[1]	70	1			T117	14		T199	28		T344	28
auto[0]	values[6]	values[2]	38	1			T26	24		T198	12		T97	2
auto[0]	values[6]	values[3]	6	1			T267	2		T103	4		-	-
auto[0]	values[6]	values[4]	8	1			T345	8		-	-		-	-
auto[0]	values[6]	values[5]	28	1			T193	10		T346	18		-	-
auto[0]	values[6]	values[6]	72	1			T44	16		T79	8		T248	18
auto[0]	values[6]	values[7]	44	1			T223	12		T288	32		-	-
auto[0]	values[7]	values[0]	46	1			T233	8		T270	10		T347	16
auto[0]	values[7]	values[1]	68	1			T47	22		T348	20		T349	4
auto[0]	values[7]	values[2]	116	1			T183	4		T100	14		T29	20
auto[0]	values[7]	values[3]	74	1			T46	10		T28	6		T53	24
auto[0]	values[7]	values[4]	14	1			T59	4		T128	10		-	-
auto[0]	values[7]	values[5]	2	1			T184	2		-	-		-	-
auto[0]	values[7]	values[6]	2	1			T222	2		-	-		-	-
auto[0]	values[7]	values[7]	138	1			T80	22		T259	14		T24	14
auto[1]	values[0]	values[2]	12	1			T190	8		T137	4		-	-
auto[1]	values[0]	values[3]	58	1			T73	32		T296	26		-	-
auto[1]	values[0]	values[4]	34	1			T204	10		T271	24		-	-
auto[1]	values[0]	values[5]	32	1			T228	32		-	-		-	-
auto[1]	values[0]	values[6]	2	1			T269	2		-	-		-	-
auto[1]	values[0]	values[7]	2	1			T209	2		-	-		-	-
auto[1]	values[1]	values[1]	4	1			T350	4		-	-		-	-
auto[1]	values[1]	values[2]	42	1			T262	14		T299	10		T295	18
auto[1]	values[1]	values[3]	22	1			T351	22		-	-		-	-
auto[1]	values[2]	values[0]	44	1			T9	10		T77	14		T279	20
auto[1]	values[2]	values[1]	24	1			T10	24		-	-		-	-
auto[1]	values[2]	values[2]	34	1			T291	34		-	-		-	-
auto[1]	values[2]	values[6]	26	1			T81	18		T286	8		-	-
auto[1]	values[3]	values[2]	24	1			T232	16		T87	8		-	-
auto[1]	values[3]	values[3]	38	1			T84	32		T247	6		-	-
auto[1]	values[3]	values[5]	26	1			T86	26		-	-		-	-
auto[1]	values[3]	values[6]	28	1			T352	28		-	-		-	-
auto[1]	values[4]	values[1]	22	1			T303	22		-	-		-	-
auto[1]	values[4]	values[2]	20	1			T88	20		-	-		-	-
auto[1]	values[4]	values[3]	32	1			T353	24		T294	8		-	-
auto[1]	values[4]	values[5]	8	1			T298	8		-	-		-	-
auto[1]	values[4]	values[6]	28	1			T207	28		-	-		-	-
auto[1]	values[5]	values[1]	12	1			T297	12		-	-		-	-
auto[1]	values[5]	values[2]	2	1			T224	2		-	-		-	-
auto[1]	values[5]	values[5]	12	1			T236	12		-	-		-	-
auto[1]	values[5]	values[6]	26	1			T214	26		-	-		-	-
auto[1]	values[5]	values[7]	18	1			T268	18		-	-		-	-
auto[1]	values[6]	values[2]	20	1			T354	20		-	-		-	-
auto[1]	values[6]	values[4]	10	1			T251	6		T280	4		-	-
auto[1]	values[6]	values[5]	8	1			T71	8		-	-		-	-
auto[1]	values[6]	values[6]	10	1			T274	10		-	-		-	-
auto[1]	values[6]	values[7]	6	1			T273	6		-	-		-	-
auto[1]	values[7]	values[1]	10	1			T85	10		-	-		-	-
auto[1]	values[7]	values[2]	28	1			T208	28		-	-		-	-
auto[1]	values[7]	values[3]	24	1			T217	24		-	-		-	-
auto[1]	values[7]	values[4]	26	1			T83	26		-	-		-	-
auto[1]	values[7]	values[7]	24	1			T235	10		T293	14		-	-