Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	10	50	83.33

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	10	50	83.33	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	132	1			T98	20		T191	10		T118	2
auto[ReadAddrCrossIntoMailbox]	14	1			T272	2		T343	4		T321	4
auto[ReadAddrCrossOutOfMailbox]	32	1			T101	2		T198	4		T277	4
auto[ReadAddrCrossAllMailbox]	32	1			T101	2		T198	2		T264	2
auto[ReadAddrOutsideMailbox]	770	1			T3	12		T5	10		T9	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

490

1

T3

6

T5

5

T9

2

auto[1]

490

1

T3

6

T5

5

T9

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	152	1			T3	4		T12	4		T82	4
read_ops[0x0b]	160	1			T5	6		T9	2		T78	2
read_ops[0x3b]	162	1			T5	2		T95	2		T96	2
read_ops[0x6b]	156	1			T3	2		T72	2		T81	4
read_ops[0xbb]	178	1			T3	6		T5	2		T9	2
read_ops[0xeb]	172	1			T10	2		T12	6		T72	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	10	50	83.33	10

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x03]]	[auto[ReadAddrCrossIntoMailbox]]	*	--	--	2
[read_ops[0x03]]	[auto[ReadAddrCrossAllMailbox]]	*	--	--	2
[read_ops[0x3b]]	[auto[ReadAddrCrossIntoMailbox] , auto[ReadAddrCrossOutOfMailbox]]	*	--	--	4
[read_ops[0x6b]]	[auto[ReadAddrCrossIntoMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	10	1			T89	2		T196	4		T355	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	10	1			T89	2		T196	4		T355	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T216	1		T343	2		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T216	1		T343	2		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	63	1			T3	2		T12	2		T82	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	63	1			T3	2		T12	2		T82	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	5	1			T98	4		T343	1		-	-
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	5	1			T98	4		T343	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T337	1		T356	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T337	1		T356	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T198	1		T272	1		T337	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T198	1		T272	1		T337	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T198	1		T216	1		T272	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T198	1		T216	1		T272	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	67	1			T5	3		T9	1		T78	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	67	1			T5	3		T9	1		T78	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T98	2		T198	2		T223	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T98	2		T198	2		T223	3
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T341	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	1	1			T341	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	72	1			T5	1		T95	1		T96	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	72	1			T5	1		T95	1		T96	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T216	1		T223	1		T234	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T216	1		T223	1		T234	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	4	1			T101	1		T272	1		T192	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T101	1		T272	1		T192	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T101	1		T216	1		T234	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T101	1		T216	1		T234	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	49	1			T3	1		T72	1		T81	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	49	1			T3	1		T72	1		T81	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	16	1			T98	2		T191	5		T118	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	16	1			T98	2		T191	5		T118	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T343	2		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T343	2		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T277	1		T343	1		T321	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T277	1		T343	1		T321	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T264	1		T216	1		T343	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	5	1			T264	1		T216	1		T343	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	63	1			T3	3		T5	1		T9	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	63	1			T3	3		T5	1		T9	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T98	2		T223	1		T89	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T98	2		T223	1		T89	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T272	1		T321	2		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T272	1		T321	2		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T198	1		T277	1		T337	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T198	1		T277	1		T337	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T277	1		T337	2		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T277	1		T337	2		-	-
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	71	1			T10	1		T12	3		T72	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	71	1			T10	1		T12	3		T72	1