Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	265414	1			T1	1		T2	1		T3	1
all_pins[1]	265414	1			T1	1		T2	1		T3	1
all_pins[2]	265414	1			T1	1		T2	1		T3	1
all_pins[3]	265414	1			T1	1		T2	1		T3	1
all_pins[4]	265414	1			T1	1		T2	1		T3	1
all_pins[5]	265414	1			T1	1		T2	1		T3	1
all_pins[6]	265414	1			T1	1		T2	1		T3	1
all_pins[7]	265414	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2122386	1			T1	8		T2	8		T3	8
values[0x1]	926	1			T33	25		T34	42		T35	17
transitions[0x0=>0x1]	700	1			T33	19		T34	35		T35	14
transitions[0x1=>0x0]	716	1			T33	20		T34	35		T35	14

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	265313	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	101	1			T34	5		T35	1		T368	2
all_pins[0]	transitions[0x0=>0x1]	71	1			T34	5		T35	1		T368	1
all_pins[0]	transitions[0x1=>0x0]	93	1			T33	4		T34	8		T368	7
all_pins[1]	values[0x0]	265291	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	123	1			T33	4		T34	8		T368	8
all_pins[1]	transitions[0x0=>0x1]	109	1			T33	4		T34	7		T368	6
all_pins[1]	transitions[0x1=>0x0]	84	1			T33	4		T35	2		T368	4
all_pins[2]	values[0x0]	265316	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	98	1			T33	4		T34	1		T35	2
all_pins[2]	transitions[0x0=>0x1]	78	1			T33	4		T34	1		T35	2
all_pins[2]	transitions[0x1=>0x0]	105	1			T33	2		T34	8		T35	4
all_pins[3]	values[0x0]	265289	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	125	1			T33	2		T34	8		T35	4
all_pins[3]	transitions[0x0=>0x1]	93	1			T34	7		T35	3		T368	11
all_pins[3]	transitions[0x1=>0x0]	99	1			T33	3		T34	4		T35	2
all_pins[4]	values[0x0]	265283	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	131	1			T33	5		T34	5		T35	3
all_pins[4]	transitions[0x0=>0x1]	100	1			T33	3		T34	4		T35	3
all_pins[4]	transitions[0x1=>0x0]	74	1			T34	4		T368	7		T371	2
all_pins[5]	values[0x0]	265309	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	105	1			T33	2		T34	5		T368	8
all_pins[5]	transitions[0x0=>0x1]	77	1			T33	2		T34	4		T368	6
all_pins[5]	transitions[0x1=>0x0]	86	1			T33	1		T34	5		T35	4
all_pins[6]	values[0x0]	265300	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	114	1			T33	1		T34	6		T35	4
all_pins[6]	transitions[0x0=>0x1]	84	1			T34	4		T35	3		T368	2
all_pins[6]	transitions[0x1=>0x0]	99	1			T33	6		T34	2		T35	2
all_pins[7]	values[0x0]	265285	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	129	1			T33	7		T34	4		T35	3
all_pins[7]	transitions[0x0=>0x1]	88	1			T33	6		T34	3		T35	2
all_pins[7]	transitions[0x1=>0x0]	76	1			T34	4		T368	1		T369	2