Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
66.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	49	79	61.72

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	49	79	61.72	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	478	1			T10	24		T72	10		T82	16
values[1]	456	1			T3	14		T5	18		T45	8
values[2]	480	1			T95	2		T185	8		T186	18
values[3]	636	1			T9	10		T12	20		T71	8
values[4]	224	1			T187	36		T188	12		T189	2
values[5]	306	1			T99	6		T117	14		T135	22
values[6]	270	1			T23	6		T190	8		T118	10
values[7]	378	1			T4	6		T183	4		T24	14

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	310	1			T72	10		T45	8		T79	8
values[1]	474	1			T82	16		T46	10		T117	14
values[2]	392	1			T3	14		T9	10		T81	18
values[3]	356	1			T4	6		T10	24		T99	6
values[4]	336	1			T12	20		T183	4		T101	6
values[5]	468	1			T44	16		T95	2		T78	16
values[6]	496	1			T191	14		T190	8		T139	28
values[7]	396	1			T5	18		T71	8		T96	12

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3158

1

T3

14

T4

6

T5

18

auto[1]

70

1

T9

4

T10

4

T73

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	49	79	61.72	49

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[5]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[values[3]]	0	1	1
[auto[0]]	[values[4]]	[values[0]]	0	1	1
[auto[1]]	[values[0]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[0]]	[values[4] , values[5] , values[6]]	--	--	3
[auto[1]]	[values[1]]	[values[1] , values[2] , values[3] , values[4]]	--	--	4
[auto[1]]	[values[1]]	[values[6]]	0	1	1
[auto[1]]	[values[2]]	[values[1]]	0	1	1
[auto[1]]	[values[2]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[2]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[3]]	[values[1]]	0	1	1
[auto[1]]	[values[3]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[3]]	[values[7]]	0	1	1
[auto[1]]	[values[4]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[4]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[6]]	[values[0]]	0	1	1
[auto[1]]	[values[6]]	[values[2]]	0	1	1
[auto[1]]	[values[6]]	[values[4] , values[5] , values[6]]	--	--	3
[auto[1]]	[values[7]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	6
[auto[1]]	[values[7]]	[values[7]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	32	1			T72	10		T79	8		T192	6
auto[0]	values[0]	values[1]	90	1			T82	16		T46	10		T193	10
auto[0]	values[0]	values[2]	32	1			T194	32		-	-		-	-
auto[0]	values[0]	values[3]	94	1			T10	20		T26	24		T59	4
auto[0]	values[0]	values[4]	58	1			T195	10		T196	28		T197	20
auto[0]	values[0]	values[5]	58	1			T78	16		T198	12		T199	28
auto[0]	values[0]	values[6]	44	1			T200	28		T201	12		T127	4
auto[0]	values[0]	values[7]	62	1			T73	30		T56	6		T202	26
auto[0]	values[1]	values[0]	36	1			T45	8		T203	14		T204	8
auto[0]	values[1]	values[1]	52	1			T205	24		T128	10		T206	18
auto[0]	values[1]	values[2]	82	1			T3	14		T207	28		T208	28
auto[0]	values[1]	values[4]	32	1			T101	6		T209	2		T210	18
auto[0]	values[1]	values[5]	88	1			T98	32		T83	24		T138	20
auto[0]	values[1]	values[6]	66	1			T191	14		T211	18		T120	10
auto[0]	values[1]	values[7]	88	1			T5	18		T96	12		T47	22
auto[0]	values[2]	values[0]	60	1			T88	16		T212	10		T213	16
auto[0]	values[2]	values[1]	80	1			T80	22		T214	26		T215	18
auto[0]	values[2]	values[2]	80	1			T84	28		T216	18		T217	24
auto[0]	values[2]	values[3]	46	1			T184	2		T218	10		T219	34
auto[0]	values[2]	values[4]	52	1			T220	8		T221	4		T222	2
auto[0]	values[2]	values[5]	76	1			T95	2		T185	8		T186	18
auto[0]	values[2]	values[6]	54	1			T223	12		T224	2		T225	6
auto[0]	values[2]	values[7]	14	1			T226	14		-	-		-	-
auto[0]	values[3]	values[0]	68	1			T227	10		T228	28		T229	2
auto[0]	values[3]	values[1]	126	1			T230	30		T231	18		T102	16
auto[0]	values[3]	values[2]	68	1			T9	6		T81	18		T232	16
auto[0]	values[3]	values[3]	88	1			T233	8		T234	18		T235	10
auto[0]	values[3]	values[4]	90	1			T12	20		T74	12		T236	12
auto[0]	values[3]	values[5]	48	1			T44	16		T237	4		T238	2
auto[0]	values[3]	values[6]	78	1			T239	24		T77	12		T240	26
auto[0]	values[3]	values[7]	54	1			T71	8		T137	4		T100	14
auto[0]	values[4]	values[1]	22	1			T241	14		T242	8		-	-
auto[0]	values[4]	values[2]	24	1			T243	24		-	-		-	-
auto[0]	values[4]	values[3]	8	1			T189	2		T28	6		-	-
auto[0]	values[4]	values[4]	12	1			T87	4		T244	8		-	-
auto[0]	values[4]	values[5]	26	1			T245	14		T246	12		-	-
auto[0]	values[4]	values[6]	64	1			T187	36		T188	12		T247	6
auto[0]	values[4]	values[7]	64	1			T248	18		T249	34		T250	2
auto[0]	values[5]	values[0]	16	1			T251	6		T252	10		-	-
auto[0]	values[5]	values[1]	32	1			T117	14		T253	18		-	-
auto[0]	values[5]	values[2]	20	1			T254	2		T255	18		-	-
auto[0]	values[5]	values[3]	44	1			T99	6		T256	14		T257	24
auto[0]	values[5]	values[4]	16	1			T258	16		-	-		-	-
auto[0]	values[5]	values[5]	64	1			T135	22		T259	14		T53	24
auto[0]	values[5]	values[6]	66	1			T139	28		T260	28		T261	10
auto[0]	values[5]	values[7]	48	1			T262	14		T103	4		T263	2
auto[0]	values[6]	values[0]	24	1			T264	2		T75	14		T265	2
auto[0]	values[6]	values[1]	30	1			T266	12		T267	2		T268	16
auto[0]	values[6]	values[2]	36	1			T269	2		T270	10		T271	24
auto[0]	values[6]	values[3]	24	1			T272	10		T273	6		T274	6
auto[0]	values[6]	values[4]	42	1			T23	6		T90	24		T97	2
auto[0]	values[6]	values[5]	26	1			T275	24		T276	2		-	-
auto[0]	values[6]	values[6]	32	1			T190	8		T118	10		T277	8
auto[0]	values[6]	values[7]	46	1			T278	26		T279	16		T280	4
auto[0]	values[7]	values[0]	54	1			T281	14		T282	10		T283	30
auto[0]	values[7]	values[1]	40	1			T284	12		T285	28		-	-
auto[0]	values[7]	values[2]	40	1			T91	32		T286	8		-	-
auto[0]	values[7]	values[3]	42	1			T4	6		T287	4		T288	32
auto[0]	values[7]	values[4]	30	1			T183	4		T76	20		T289	6
auto[0]	values[7]	values[5]	74	1			T24	14		T290	4		T291	34
auto[0]	values[7]	values[6]	88	1			T25	4		T29	20		T86	24
auto[0]	values[7]	values[7]	8	1			T292	8		-	-		-	-
auto[1]	values[0]	values[3]	6	1			T10	4		T293	2		-	-
auto[1]	values[0]	values[7]	2	1			T73	2		-	-		-	-
auto[1]	values[1]	values[0]	4	1			T204	2		T294	2		-	-
auto[1]	values[1]	values[5]	2	1			T83	2		-	-		-	-
auto[1]	values[1]	values[7]	6	1			T85	2		T295	4		-	-
auto[1]	values[2]	values[0]	12	1			T88	4		T296	8		-	-
auto[1]	values[2]	values[2]	4	1			T84	4		-	-		-	-
auto[1]	values[2]	values[5]	2	1			T297	2		-	-		-	-
auto[1]	values[3]	values[0]	4	1			T228	4		-	-		-	-
auto[1]	values[3]	values[2]	6	1			T9	4		T298	2		-	-
auto[1]	values[3]	values[5]	4	1			T299	4		-	-		-	-
auto[1]	values[3]	values[6]	2	1			T77	2		-	-		-	-
auto[1]	values[4]	values[4]	4	1			T87	4		-	-		-	-
auto[1]	values[6]	values[1]	2	1			T268	2		-	-		-	-
auto[1]	values[6]	values[3]	4	1			T274	4		-	-		-	-
auto[1]	values[6]	values[7]	4	1			T279	4		-	-		-	-
auto[1]	values[7]	values[6]	2	1			T86	2		-	-		-	-