Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1510

1

T1

21

T13

8

T14

24

auto[1]

1396

1

T1

12

T13

7

T14

24

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

677

1

T13

11

T65

15

T66

12

auto[1]

2229

1

T1

33

T13

4

T14

48

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2621

1

T1

33

T13

13

T14

48

auto[1]

285

1

T13

2

T65

4

T66

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	628	1			T1	10		T13	6		T14	13
valid[1]	577	1			T1	9		T13	5		T14	5
valid[2]	583	1			T1	6		T14	9		T21	11
valid[3]	557	1			T1	3		T13	2		T14	9
valid[4]	561	1			T1	5		T13	2		T14	12

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	45	1			T13	3		T65	1		T66	1
auto[0]	auto[0]	valid[0]	auto[1]	244	1			T1	9		T13	1		T14	5
auto[0]	auto[0]	valid[1]	auto[0]	43	1			T13	1		T65	3		T110	1
auto[0]	auto[0]	valid[1]	auto[1]	231	1			T1	4		T13	1		T14	2
auto[0]	auto[0]	valid[2]	auto[0]	35	1			T65	2		T110	1		T111	1
auto[0]	auto[0]	valid[2]	auto[1]	231	1			T1	2		T14	6		T21	6
auto[0]	auto[0]	valid[3]	auto[0]	42	1			T65	1		T110	3		T111	1
auto[0]	auto[0]	valid[3]	auto[1]	227	1			T1	2		T13	1		T14	5
auto[0]	auto[0]	valid[4]	auto[0]	34	1			T65	1		T110	2		T382	1
auto[0]	auto[0]	valid[4]	auto[1]	227	1			T1	4		T14	6		T21	2
auto[0]	auto[1]	valid[0]	auto[0]	38	1			T13	1		T65	1		T66	1
auto[0]	auto[1]	valid[0]	auto[1]	232	1			T1	1		T13	1		T14	8
auto[0]	auto[1]	valid[1]	auto[0]	49	1			T13	2		T66	2		T110	2
auto[0]	auto[1]	valid[1]	auto[1]	205	1			T1	5		T14	3		T21	4
auto[0]	auto[1]	valid[2]	auto[0]	31	1			T68	1		T113	1		T383	1
auto[0]	auto[1]	valid[2]	auto[1]	226	1			T1	4		T14	3		T21	5
auto[0]	auto[1]	valid[3]	auto[0]	33	1			T65	2		T111	1		T382	2
auto[0]	auto[1]	valid[3]	auto[1]	201	1			T1	1		T14	4		T21	9
auto[0]	auto[1]	valid[4]	auto[0]	42	1			T13	2		T66	2		T68	1
auto[0]	auto[1]	valid[4]	auto[1]	205	1			T1	1		T14	6		T21	4
auto[1]	auto[0]	valid[0]	auto[0]	37	1			T66	1		T110	1		T113	1
auto[1]	auto[0]	valid[1]	auto[0]	28	1			T13	1		T70	1		T110	1
auto[1]	auto[0]	valid[2]	auto[0]	33	1			T113	1		T112	2		T386	1
auto[1]	auto[0]	valid[3]	auto[0]	29	1			T110	1		T113	1		T399	1
auto[1]	auto[0]	valid[4]	auto[0]	24	1			T110	1		T111	1		T381	1
auto[1]	auto[1]	valid[0]	auto[0]	32	1			T65	1		T111	1		T381	1
auto[1]	auto[1]	valid[1]	auto[0]	21	1			T382	2		T112	1		T386	1
auto[1]	auto[1]	valid[2]	auto[0]	27	1			T65	1		T66	3		T110	1
auto[1]	auto[1]	valid[3]	auto[0]	25	1			T13	1		T65	1		T66	2
auto[1]	auto[1]	valid[4]	auto[0]	29	1			T65	1		T382	2		T112	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal