Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17571

1

T13

334

T18

17

T19

9

auto[1]

21125

1

T1

483

T13

37

T14

585

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31894

1

T1

483

T13

249

T14

585

auto[1]

6802

1

T13

122

T18

6

T19

4

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	20188	1			T1	265		T13	192		T14	320
others[1]	3247	1			T1	34		T13	34		T14	49
others[2]	3269	1			T1	35		T13	29		T14	57
others[3]	3636	1			T1	46		T13	27		T14	40
interest[1]	2112	1			T1	34		T13	22		T14	28
interest[4]	13328	1			T1	164		T13	120		T14	214
interest[64]	6244	1			T1	69		T13	67		T14	91

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5551	1			T13	99		T18	8		T19	2
auto[0]	auto[0]	others[1]	897	1			T13	21		T18	1		T65	26
auto[0]	auto[0]	others[2]	921	1			T13	14		T19	2		T65	28
auto[0]	auto[0]	others[3]	1041	1			T13	13		T18	2		T65	30
auto[0]	auto[0]	interest[1]	584	1			T13	17		T19	1		T65	14
auto[0]	auto[0]	interest[4]	3608	1			T13	65		T18	5		T19	1
auto[0]	auto[0]	interest[64]	1775	1			T13	48		T22	1		T65	55
auto[0]	auto[1]	others[0]	11101	1			T1	265		T13	19		T14	320
auto[0]	auto[1]	others[1]	1810	1			T1	34		T13	4		T14	49
auto[0]	auto[1]	others[2]	1750	1			T1	35		T13	5		T14	57
auto[0]	auto[1]	others[3]	1952	1			T1	46		T13	5		T14	40
auto[0]	auto[1]	interest[1]	1148	1			T1	34		T13	2		T14	28
auto[0]	auto[1]	interest[4]	7410	1			T1	164		T13	11		T14	214
auto[0]	auto[1]	interest[64]	3364	1			T1	69		T13	2		T14	91
auto[1]	auto[0]	others[0]	3536	1			T13	74		T18	1		T19	3
auto[1]	auto[0]	others[1]	540	1			T13	9		T18	1		T19	1
auto[1]	auto[0]	others[2]	598	1			T13	10		T18	1		T22	1
auto[1]	auto[0]	others[3]	643	1			T13	9		T18	1		T22	1
auto[1]	auto[0]	interest[1]	380	1			T13	3		T18	1		T22	2
auto[1]	auto[0]	interest[4]	2310	1			T13	44		T18	1		T19	2
auto[1]	auto[0]	interest[64]	1105	1			T13	17		T18	1		T65	20

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal