Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	463	1			T33	11		T34	24		T35	8
all_values[1]	463	1			T33	11		T34	24		T35	8
all_values[2]	463	1			T33	11		T34	24		T35	8
all_values[3]	463	1			T33	11		T34	24		T35	8
all_values[4]	463	1			T33	11		T34	24		T35	8
all_values[5]	463	1			T33	11		T34	24		T35	8
all_values[6]	463	1			T33	11		T34	24		T35	8
all_values[7]	463	1			T33	11		T34	24		T35	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1979

1

T33

52

T34

105

T35

43

auto[1]

1725

1

T33

36

T34

87

T35

21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1413

1

T33

31

T34

73

T35

23

auto[1]

2291

1

T33

57

T34

119

T35

41

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2084

1

T33

47

T34

100

T35

36

auto[1]

1620

1

T33

41

T34

92

T35

28

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	86	1			T33	5		T34	2		T35	3
all_values[0]	auto[0]	auto[0]	auto[1]	42	1			T33	1		T34	2		T368	1
all_values[0]	auto[0]	auto[1]	auto[0]	102	1			T33	3		T34	5		T35	2
all_values[0]	auto[0]	auto[1]	auto[1]	39	1			T34	2		T369	1		T370	1
all_values[0]	auto[1]	auto[0]	auto[1]	112	1			T33	1		T34	9		T35	2
all_values[0]	auto[1]	auto[1]	auto[1]	82	1			T33	1		T34	4		T35	1
all_values[1]	auto[0]	auto[0]	auto[0]	85	1			T33	1		T34	2		T35	3
all_values[1]	auto[0]	auto[0]	auto[1]	58	1			T33	2		T34	2		T35	1
all_values[1]	auto[0]	auto[1]	auto[0]	53	1			T33	1		T34	4		T368	3
all_values[1]	auto[0]	auto[1]	auto[1]	52	1			T33	2		T34	1		T368	3
all_values[1]	auto[1]	auto[0]	auto[1]	118	1			T33	3		T34	4		T35	3
all_values[1]	auto[1]	auto[1]	auto[1]	97	1			T33	2		T34	11		T35	1
all_values[2]	auto[0]	auto[0]	auto[0]	105	1			T33	5		T34	5		T35	1
all_values[2]	auto[0]	auto[0]	auto[1]	38	1			T34	2		T35	1		T368	3
all_values[2]	auto[0]	auto[1]	auto[0]	77	1			T34	7		T35	2		T368	7
all_values[2]	auto[0]	auto[1]	auto[1]	39	1			T33	2		T35	1		T368	1
all_values[2]	auto[1]	auto[0]	auto[1]	115	1			T33	2		T34	6		T35	1
all_values[2]	auto[1]	auto[1]	auto[1]	89	1			T33	2		T34	4		T35	2
all_values[3]	auto[0]	auto[0]	auto[0]	79	1			T33	4		T34	7		T35	3
all_values[3]	auto[0]	auto[0]	auto[1]	42	1			T35	1		T368	2		T371	2
all_values[3]	auto[0]	auto[1]	auto[0]	80	1			T33	1		T34	6		T368	3
all_values[3]	auto[0]	auto[1]	auto[1]	52	1			T33	1		T34	2		T35	2
all_values[3]	auto[1]	auto[0]	auto[1]	119	1			T33	3		T34	4		T35	1
all_values[3]	auto[1]	auto[1]	auto[1]	91	1			T33	2		T34	5		T35	1
all_values[4]	auto[0]	auto[0]	auto[0]	82	1			T33	1		T34	4		T368	3
all_values[4]	auto[0]	auto[0]	auto[1]	37	1			T33	3		T34	2		T35	1
all_values[4]	auto[0]	auto[1]	auto[0]	74	1			T34	3		T35	2		T368	4
all_values[4]	auto[0]	auto[1]	auto[1]	63	1			T33	1		T34	1		T35	1
all_values[4]	auto[1]	auto[0]	auto[1]	104	1			T33	4		T34	10		T35	3
all_values[4]	auto[1]	auto[1]	auto[1]	103	1			T33	2		T34	4		T35	1
all_values[5]	auto[0]	auto[0]	auto[0]	161	1			T33	4		T34	10		T35	4
all_values[5]	auto[0]	auto[1]	auto[0]	113	1			T33	1		T34	4		T35	1
all_values[5]	auto[1]	auto[0]	auto[1]	99	1			T33	4		T34	4		T35	2
all_values[5]	auto[1]	auto[1]	auto[1]	90	1			T33	2		T34	6		T35	1
all_values[6]	auto[0]	auto[0]	auto[0]	94	1			T33	3		T34	6		T368	5
all_values[6]	auto[0]	auto[0]	auto[1]	57	1			T33	1		T34	4		T35	2
all_values[6]	auto[0]	auto[1]	auto[0]	68	1			T33	2		T34	1		T368	4
all_values[6]	auto[0]	auto[1]	auto[1]	44	1			T33	1		T34	4		T35	1
all_values[6]	auto[1]	auto[0]	auto[1]	106	1			T33	1		T34	6		T35	4
all_values[6]	auto[1]	auto[1]	auto[1]	94	1			T33	3		T34	3		T35	1
all_values[7]	auto[0]	auto[0]	auto[0]	87	1			T34	3		T35	2		T368	4
all_values[7]	auto[0]	auto[0]	auto[1]	50	1			T33	1		T34	2		T35	1
all_values[7]	auto[0]	auto[1]	auto[0]	67	1			T34	4		T368	4		T371	1
all_values[7]	auto[0]	auto[1]	auto[1]	58	1			T33	1		T34	3		T35	1
all_values[7]	auto[1]	auto[0]	auto[1]	103	1			T33	3		T34	9		T35	4
all_values[7]	auto[1]	auto[1]	auto[1]	98	1			T33	6		T34	3		T368	8

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal