Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	291140	1			T2	1		T3	1		T7	1
all_values[1]	291140	1			T2	1		T3	1		T7	1
all_values[2]	291140	1			T2	1		T3	1		T7	1
all_values[3]	291140	1			T2	1		T3	1		T7	1
all_values[4]	291140	1			T2	1		T3	1		T7	1
all_values[5]	291140	1			T2	1		T3	1		T7	1
all_values[6]	291140	1			T2	1		T3	1		T7	1
all_values[7]	291140	1			T2	1		T3	1		T7	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2326735

1

T2

8

T3

8

T7

8

auto[1]

2385

1

T18

58

T20

58

T22

48

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2326921

1

T2

8

T3

8

T7

8

auto[1]

2199

1

T18

32

T20

62

T22

28

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	290717	1			T2	1		T3	1		T7	1
all_values[0]	auto[0]	auto[1]	137	1			T18	1		T20	6		T22	1
all_values[0]	auto[1]	auto[0]	156	1			T18	6		T20	2		T22	4
all_values[0]	auto[1]	auto[1]	130	1			T18	3		T20	2		T22	3
all_values[1]	auto[0]	auto[0]	290712	1			T2	1		T3	1		T7	1
all_values[1]	auto[0]	auto[1]	145	1			T18	4		T20	7		T22	3
all_values[1]	auto[1]	auto[0]	152	1			T18	2		T20	3		T22	2
all_values[1]	auto[1]	auto[1]	131	1			T20	2		T22	1		T345	5
all_values[2]	auto[0]	auto[0]	290732	1			T2	1		T3	1		T7	1
all_values[2]	auto[0]	auto[1]	121	1			T18	1		T20	3		T22	1
all_values[2]	auto[1]	auto[0]	168	1			T18	7		T20	4		T22	5
all_values[2]	auto[1]	auto[1]	119	1			T18	3		T20	9		T22	1
all_values[3]	auto[0]	auto[0]	290695	1			T2	1		T3	1		T7	1
all_values[3]	auto[0]	auto[1]	133	1			T18	3		T20	5		T22	2
all_values[3]	auto[1]	auto[0]	194	1			T18	6		T20	2		T22	6
all_values[3]	auto[1]	auto[1]	118	1			T20	4		T22	1		T345	5
all_values[4]	auto[0]	auto[0]	290711	1			T2	1		T3	1		T7	1
all_values[4]	auto[0]	auto[1]	119	1			T18	3		T20	3		T22	1
all_values[4]	auto[1]	auto[0]	202	1			T18	2		T20	9		T22	5
all_values[4]	auto[1]	auto[1]	108	1			T18	3		T20	1		T22	3
all_values[5]	auto[0]	auto[0]	290526	1			T2	1		T3	1		T7	1
all_values[5]	auto[0]	auto[1]	293	1			T18	1		T20	5		T22	2
all_values[5]	auto[1]	auto[0]	199	1			T18	5		T20	10		T22	4
all_values[5]	auto[1]	auto[1]	122	1			T18	3		T22	3		T345	3
all_values[6]	auto[0]	auto[0]	290697	1			T2	1		T3	1		T7	1
all_values[6]	auto[0]	auto[1]	145	1			T18	1		T20	6		T22	2
all_values[6]	auto[1]	auto[0]	178	1			T18	8		T20	6		T22	5
all_values[6]	auto[1]	auto[1]	120	1			T18	1		T22	2		T345	3
all_values[7]	auto[0]	auto[0]	290722	1			T2	1		T3	1		T7	1
all_values[7]	auto[0]	auto[1]	130	1			T18	2		T20	7		T22	1
all_values[7]	auto[1]	auto[0]	160	1			T18	6		T20	2		T22	2
all_values[7]	auto[1]	auto[1]	128	1			T18	3		T20	2		T22	1