Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	34	50	59.52

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	29	19	39.58	100	1	1	0
cr_modeXdummyXnum_lanes	36	5	31	86.11	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1164	1			T2	6		T3	2		T4	4
auto[SpiFlashAddrCfg]	869	1			T2	8		T4	2		T9	4
auto[SpiFlashAddr3b]	1065	1			T2	6		T5	8		T9	4
auto[SpiFlashAddr4b]	781	1			T5	6		T12	4		T87	5

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3035

1

T2

20

T3

2

T4

6

auto[1]

844

1

T67

2

T68

12

T64

22

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2020

1

T2

14

T4

2

T5

8

auto[1]

1859

1

T2

6

T3

2

T4

4

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1591	1			T2	8		T3	2		T4	6
values[1]	72	1			T82	3		T65	2		T167	4
values[2]	195	1			T2	4		T95	2		T100	4
values[3]	190	1			T87	4		T64	6		T37	4
values[4]	193	1			T2	4		T9	2		T12	2
values[5]	204	1			T9	4		T95	4		T88	6
values[6]	140	1			T5	4		T36	4		T68	2
values[7]	189	1			T12	2		T74	2		T224	6
values[8]	1105	1			T2	4		T5	6		T9	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3300

1

T2

20

T3

2

T4

6

auto[1]

579

1

T87

9

T82

11

T88

16

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3749

1

T2

20

T3

2

T4

6

write

130

1

T64

4

T65

4

T66

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1786

1

T2

8

T5

8

T8

20

valids[0x1]

2093

1

T2

12

T3

2

T4

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	190	1			T3	2		T5	2		T12	2
internal_process_ops[0x5a]	230	1			T5	4		T68	2		T72	2
internal_process_ops[0x05]	194	1			T2	2		T4	4		T5	4
internal_process_ops[0x35]	232	1			T5	4		T71	2		T65	2
internal_process_ops[0x15]	192	1			T2	2		T36	2		T64	4
internal_process_ops[0x03]	266	1			T2	4		T4	2		T36	4
internal_process_ops[0x0b]	242	1			T9	2		T100	4		T88	5
internal_process_ops[0x3b]	303	1			T68	2		T37	4		T82	5
internal_process_ops[0x6b]	250	1			T5	2		T87	5		T68	2
internal_process_ops[0xbb]	232	1			T9	4		T12	4		T96	2
internal_process_ops[0xeb]	268	1			T2	2		T5	4		T9	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3849

1

T2

20

T3

2

T4

6

auto[1]

30

1

T64

4

T65

4

T69

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3879

1

T2

20

T3

2

T4

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	29	19	39.58	29
Automatically Generated Cross Bins	48	29	19	39.58	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	[auto[SpiFlashAddrDisabled]]	*	[auto[0]]	--	--	2
[auto[1]]	[write]	*	*	*	--	--	16

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddrCfg] , auto[SpiFlashAddr3b] , auto[SpiFlashAddr4b]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

936

1

T2

6

T3

2

T4

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

182

1

T68

2

T64

6

T71

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

412

1

T2

8

T4

2

T9

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

246

1

T68

4

T64

4

T71

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

612

1

T2

6

T5

8

T9

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

230

1

T68

4

T64

4

T71

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

396

1

T5

6

T12

4

T96

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

156

1

T67

2

T68

2

T64

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

40

1

T200

2

T232

8

T244

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

6

1

T76

6

-

-

-

-

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

22

1

T112

2

T263

2

T221

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

14

1

T64

4

T65

4

T69

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

22

1

T52

2

T252

2

T232

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

2

1

T78

2

-

-

-

-

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

16

1

T66

2

T52

2

T281

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

8

1

T75

4

T77

4

-

-

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

175

1

T82

5

T88

6

T53

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

199

1

T87

4

T82

3

T89

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

205

1

T87

5

T82

3

T88

10

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	5	31	86.11	5

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0] , values[1]]	[valids[0x0]]	--	--	2
[auto[1]]	[values[4]]	[valids[0x1]]	0	1	1
[auto[1]]	[values[6]]	[valids[0x1]]	0	1	1

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	306	1			T5	2		T8	20		T11	2
auto[0]	values[0]	valids[0x1]	1228	1			T2	8		T3	2		T4	6
auto[0]	values[1]	valids[0x1]	50	1			T65	2		T167	4		T252	4
auto[0]	values[2]	valids[0x0]	102	1			T2	4		T74	2		T171	4
auto[0]	values[2]	valids[0x1]	48	1			T95	2		T100	4		T256	4
auto[0]	values[3]	valids[0x0]	110	1			T64	6		T37	4		T279	10
auto[0]	values[3]	valids[0x1]	40	1			T72	4		T74	4		T260	2
auto[0]	values[4]	valids[0x0]	106	1			T9	2		T12	2		T100	2
auto[0]	values[4]	valids[0x1]	56	1			T2	4		T247	2		T93	4
auto[0]	values[5]	valids[0x0]	120	1			T9	4		T95	4		T66	4
auto[0]	values[5]	valids[0x1]	46	1			T66	4		T213	2		T173	2
auto[0]	values[6]	valids[0x0]	40	1			T96	2		T70	2		T273	2
auto[0]	values[6]	valids[0x1]	62	1			T5	4		T36	4		T68	2
auto[0]	values[7]	valids[0x0]	88	1			T12	2		T74	2		T224	6
auto[0]	values[7]	valids[0x1]	42	1			T197	6		T173	4		T227	6
auto[0]	values[8]	valids[0x0]	548	1			T2	4		T5	6		T12	6
auto[0]	values[8]	valids[0x1]	308	1			T9	2		T68	2		T64	2
auto[1]	values[0]	valids[0x1]	57	1			T282	2		T283	3		T284	2
auto[1]	values[1]	valids[0x1]	22	1			T82	3		T53	2		T285	1
auto[1]	values[2]	valids[0x0]	34	1			T286	6		T287	4		T288	4
auto[1]	values[2]	valids[0x1]	11	1			T53	1		T289	7		T290	2
auto[1]	values[3]	valids[0x0]	16	1			T87	4		T283	3		T291	4
auto[1]	values[3]	valids[0x1]	24	1			T88	2		T89	7		T292	5
auto[1]	values[4]	valids[0x0]	31	1			T82	3		T293	5		T282	7
auto[1]	values[5]	valids[0x0]	27	1			T88	6		T89	3		T53	2
auto[1]	values[5]	valids[0x1]	11	1			T284	2		T294	1		T295	8
auto[1]	values[6]	valids[0x0]	38	1			T283	3		T288	3		T296	7
auto[1]	values[7]	valids[0x0]	42	1			T293	2		T286	5		T284	3
auto[1]	values[7]	valids[0x1]	17	1			T287	4		T297	5		T290	8
auto[1]	values[8]	valids[0x0]	178	1			T87	5		T82	5		T88	3
auto[1]	values[8]	valids[0x1]	71	1			T88	5		T99	11		T298	2