Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1816225 1 T2 1 T3 403 T4 6943


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1659001 1 T2 1 T3 403 T4 5663
auto[1] 157224 1 T4 1280 T5 5558 T36 1280


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 400661 1 T2 1 T3 46 T4 1181
auto[524288:1048575] 207276 1 T3 96 T4 1115 T8 9
auto[1048576:1572863] 199015 1 T4 181 T8 1930 T9 15463
auto[1572864:2097151] 191672 1 T3 179 T4 1210 T8 5
auto[2097152:2621439] 234339 1 T3 82 T4 1967 T8 58
auto[2621440:3145727] 224264 1 T4 678 T8 9 T11 375
auto[3145728:3670015] 180848 1 T4 239 T8 897 T9 1604
auto[3670016:4194303] 178150 1 T4 372 T8 1 T9 1282


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 171460 1 T2 1 T3 8 T4 1420
auto[1] 1644765 1 T3 395 T4 5523 T8 2888


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1816225 1 T2 1 T3 403 T4 6943


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 290056 1 T2 1 T3 46 T4 1055
auto[0] auto[0] auto[0:524287] auto[1] 110605 1 T4 126 T5 5558 T36 1280
auto[0] auto[0] auto[524288:1048575] auto[0] 204053 1 T3 96 T4 987 T8 9
auto[0] auto[0] auto[524288:1048575] auto[1] 3223 1 T4 128 T160 5 T161 527
auto[0] auto[0] auto[1048576:1572863] auto[0] 194781 1 T4 181 T8 1930 T9 15463
auto[0] auto[0] auto[1048576:1572863] auto[1] 4234 1 T160 3 T161 2702 T162 533
auto[0] auto[0] auto[1572864:2097151] auto[0] 181989 1 T3 179 T4 699 T8 5
auto[0] auto[0] auto[1572864:2097151] auto[1] 9683 1 T4 511 T122 2342 T38 1
auto[0] auto[0] auto[2097152:2621439] auto[0] 225370 1 T3 82 T4 1454 T8 58
auto[0] auto[0] auto[2097152:2621439] auto[1] 8969 1 T4 513 T163 513 T38 284
auto[0] auto[0] auto[2621440:3145727] auto[0] 217562 1 T4 678 T8 9 T11 375
auto[0] auto[0] auto[2621440:3145727] auto[1] 6702 1 T38 228 T161 127 T164 2
auto[0] auto[0] auto[3145728:3670015] auto[0] 176424 1 T4 238 T8 897 T9 1604
auto[0] auto[0] auto[3145728:3670015] auto[1] 4424 1 T4 1 T165 4 T161 2698
auto[0] auto[0] auto[3670016:4194303] auto[0] 168766 1 T4 371 T8 1 T9 1282
auto[0] auto[0] auto[3670016:4194303] auto[1] 9384 1 T4 1 T122 1 T165 1


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 171460 1 T2 1 T3 8 T4 1420
auto[0] auto[0] auto[1] 1644765 1 T3 395 T4 5523 T8 2888

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