Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	31	97	75.78

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	31	97	75.78	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2456

1

T2

20

T3

2

T4

6

auto[1]

844

1

T67

2

T68

12

T64

22

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	376	1			T67	2		T68	12		T64	22
values[1]	368	1			T72	18		T166	2		T247	12
values[2]	274	1			T96	8		T122	2		T74	18
values[3]	442	1			T3	2		T8	20		T37	6
values[4]	446	1			T5	26		T12	12		T230	16
values[5]	566	1			T2	20		T36	14		T71	14
values[6]	438	1			T4	6		T9	8		T169	2
values[7]	390	1			T11	2		T81	12		T163	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	364	1			T2	20		T8	20		T11	2
values[1]	538	1			T4	6		T5	26		T64	22
values[2]	412	1			T67	2		T74	18		T52	10
values[3]	366	1			T9	8		T81	12		T96	8
values[4]	340	1			T68	12		T73	20		T168	4
values[5]	424	1			T3	2		T36	14		T72	18
values[6]	444	1			T12	12		T37	6		T95	6
values[7]	412	1			T25	8		T250	6		T200	10

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	31	97	75.78	31

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[1]]	0	1	1
[auto[0]]	[values[6]]	[values[0]]	0	1	1
[auto[1]]	[values[0]]	[values[0]]	0	1	1
[auto[1]]	[values[0]]	[values[5]]	0	1	1
[auto[1]]	[values[0]]	[values[7]]	0	1	1
[auto[1]]	[values[1]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[1]]	[values[4]]	0	1	1
[auto[1]]	[values[1]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[2]]	[values[0]]	0	1	1
[auto[1]]	[values[2]]	[values[4] , values[5] , values[6] , values[7]]	--	--	4
[auto[1]]	[values[3]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[3]]	[values[6]]	0	1	1
[auto[1]]	[values[4]]	[values[2]]	0	1	1
[auto[1]]	[values[4]]	[values[4] , values[5] , values[6] , values[7]]	--	--	4
[auto[1]]	[values[5]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[6]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[6]]	[values[7]]	0	1	1
[auto[1]]	[values[7]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[7]]	[values[4]]	0	1	1

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	34	1			T240	22		T172	12		-	-
auto[0]	values[0]	values[2]	46	1			T299	2		T300	2		T301	16
auto[0]	values[0]	values[3]	12	1			T112	12		-	-		-	-
auto[0]	values[0]	values[4]	4	1			T90	2		T186	2		-	-
auto[0]	values[0]	values[5]	16	1			T115	16		-	-		-	-
auto[0]	values[0]	values[6]	34	1			T39	6		T221	6		T302	22
auto[0]	values[0]	values[7]	60	1			T25	8		T173	26		T303	16
auto[0]	values[1]	values[0]	16	1			T280	2		T243	14		-	-
auto[0]	values[1]	values[1]	46	1			T258	8		T164	6		T304	12
auto[0]	values[1]	values[2]	26	1			T259	26		-	-		-	-
auto[0]	values[1]	values[3]	44	1			T253	18		T305	2		T306	24
auto[0]	values[1]	values[4]	12	1			T247	12		-	-		-	-
auto[0]	values[1]	values[5]	56	1			T279	26		T201	18		T192	12
auto[0]	values[1]	values[6]	66	1			T166	2		T94	8		T246	26
auto[0]	values[1]	values[7]	38	1			T235	4		T276	8		T307	6
auto[0]	values[2]	values[0]	20	1			T97	20		-	-		-	-
auto[0]	values[2]	values[1]	12	1			T308	12		-	-		-	-
auto[0]	values[2]	values[2]	6	1			T91	6		-	-		-	-
auto[0]	values[2]	values[3]	16	1			T96	8		T222	8		-	-
auto[0]	values[2]	values[4]	78	1			T244	20		T86	12		T309	20
auto[0]	values[2]	values[5]	54	1			T266	6		T165	4		T93	22
auto[0]	values[2]	values[6]	30	1			T122	2		T66	26		T249	2
auto[0]	values[2]	values[7]	20	1			T250	6		T271	8		T310	6
auto[0]	values[3]	values[0]	72	1			T8	20		T182	26		T311	16
auto[0]	values[3]	values[1]	64	1			T161	14		T277	16		T211	34
auto[0]	values[3]	values[2]	78	1			T52	10		T219	12		T264	10
auto[0]	values[3]	values[3]	42	1			T46	10		T252	14		T228	18
auto[0]	values[3]	values[4]	10	1			T255	4		T262	6		-	-
auto[0]	values[3]	values[5]	2	1			T3	2		-	-		-	-
auto[0]	values[3]	values[6]	12	1			T37	6		T95	6		-	-
auto[0]	values[3]	values[7]	22	1			T312	2		T313	20		-	-
auto[0]	values[4]	values[0]	8	1			T92	4		T181	4		-	-
auto[0]	values[4]	values[1]	82	1			T5	26		T170	36		T24	4
auto[0]	values[4]	values[2]	90	1			T213	18		T281	24		T229	2
auto[0]	values[4]	values[3]	2	1			T205	2		-	-		-	-
auto[0]	values[4]	values[4]	54	1			T256	14		T199	2		T233	30
auto[0]	values[4]	values[5]	18	1			T214	4		T183	10		T314	4
auto[0]	values[4]	values[6]	58	1			T12	12		T230	16		T315	4
auto[0]	values[4]	values[7]	60	1			T160	6		T273	14		T316	10
auto[0]	values[5]	values[0]	90	1			T2	20		T180	4		T232	26
auto[0]	values[5]	values[1]	122	1			T317	20		T191	12		T318	22
auto[0]	values[5]	values[2]	24	1			T254	8		T319	16		-	-
auto[0]	values[5]	values[3]	48	1			T261	18		T320	30		-	-
auto[0]	values[5]	values[4]	72	1			T38	26		T198	12		T113	2
auto[0]	values[5]	values[5]	56	1			T36	14		T321	6		T322	18
auto[0]	values[5]	values[6]	34	1			T242	34		-	-		-	-
auto[0]	values[5]	values[7]	16	1			T323	16		-	-		-	-
auto[0]	values[6]	values[1]	62	1			T4	6		T188	14		T116	12
auto[0]	values[6]	values[2]	6	1			T234	6		-	-		-	-
auto[0]	values[6]	values[3]	62	1			T9	8		T218	30		T324	20
auto[0]	values[6]	values[4]	2	1			T169	2		-	-		-	-
auto[0]	values[6]	values[5]	66	1			T196	32		T202	4		T325	6
auto[0]	values[6]	values[6]	56	1			T208	14		T274	2		T326	14
auto[0]	values[6]	values[7]	32	1			T200	10		T327	2		T175	20
auto[0]	values[7]	values[0]	34	1			T11	2		T163	2		T328	10
auto[0]	values[7]	values[1]	36	1			T162	14		T329	12		T330	10
auto[0]	values[7]	values[2]	74	1			T260	38		T275	18		T176	6
auto[0]	values[7]	values[3]	12	1			T81	12		-	-		-	-
auto[0]	values[7]	values[4]	10	1			T187	10		-	-		-	-
auto[0]	values[7]	values[5]	20	1			T226	2		T331	18		-	-
auto[0]	values[7]	values[6]	54	1			T26	6		T227	26		T267	12
auto[0]	values[7]	values[7]	48	1			T236	18		T185	20		T332	10
auto[1]	values[0]	values[1]	52	1			T64	22		T100	16		T80	14
auto[1]	values[0]	values[2]	2	1			T67	2		-	-		-	-
auto[1]	values[0]	values[3]	34	1			T65	34		-	-		-	-
auto[1]	values[0]	values[4]	16	1			T68	12		T168	4		-	-
auto[1]	values[0]	values[6]	66	1			T174	24		T333	20		T334	22
auto[1]	values[1]	values[2]	4	1			T206	4		-	-		-	-
auto[1]	values[1]	values[3]	16	1			T79	16		-	-		-	-
auto[1]	values[1]	values[5]	44	1			T72	18		T76	26		-	-
auto[1]	values[2]	values[1]	12	1			T70	12		-	-		-	-
auto[1]	values[2]	values[2]	22	1			T74	18		T335	4		-	-
auto[1]	values[2]	values[3]	4	1			T237	4		-	-		-	-
auto[1]	values[3]	values[2]	22	1			T336	22		-	-		-	-
auto[1]	values[3]	values[3]	20	1			T272	20		-	-		-	-
auto[1]	values[3]	values[4]	24	1			T73	20		T270	4		-	-
auto[1]	values[3]	values[5]	8	1			T171	8		-	-		-	-
auto[1]	values[3]	values[7]	66	1			T216	16		T77	20		T78	18
auto[1]	values[4]	values[0]	22	1			T337	22		-	-		-	-
auto[1]	values[4]	values[1]	36	1			T197	36		-	-		-	-
auto[1]	values[4]	values[3]	16	1			T338	16		-	-		-	-
auto[1]	values[5]	values[0]	38	1			T224	26		T167	12		-	-
auto[1]	values[5]	values[1]	14	1			T71	14		-	-		-	-
auto[1]	values[5]	values[2]	12	1			T210	12		-	-		-	-
auto[1]	values[5]	values[3]	2	1			T339	2		-	-		-	-
auto[1]	values[5]	values[4]	8	1			T225	8		-	-		-	-
auto[1]	values[5]	values[5]	30	1			T184	30		-	-		-	-
auto[1]	values[6]	values[0]	16	1			T251	2		T340	14		-	-
auto[1]	values[6]	values[3]	28	1			T212	28		-	-		-	-
auto[1]	values[6]	values[4]	50	1			T245	18		T203	32		-	-
auto[1]	values[6]	values[5]	30	1			T69	30		-	-		-	-
auto[1]	values[6]	values[6]	28	1			T341	28		-	-		-	-
auto[1]	values[7]	values[0]	14	1			T75	14		-	-		-	-
auto[1]	values[7]	values[3]	8	1			T342	8		-	-		-	-
auto[1]	values[7]	values[5]	24	1			T343	24		-	-		-	-
auto[1]	values[7]	values[6]	6	1			T344	6		-	-		-	-
auto[1]	values[7]	values[7]	50	1			T238	18		T189	32		-	-