Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
89.04	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	8	52	86.67

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	8	52	86.67	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	96	1			T279	4		T235	2		T253	2
auto[ReadAddrCrossIntoMailbox]	30	1			T9	4		T249	2		T279	2
auto[ReadAddrCrossOutOfMailbox]	12	1			T279	6		T278	2		T234	4
auto[ReadAddrCrossAllMailbox]	28	1			T95	2		T279	8		T235	2
auto[ReadAddrOutsideMailbox]	800	1			T2	6		T4	2		T5	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

483

1

T2

3

T4

1

T5

3

auto[1]

483

1

T2

3

T4

1

T5

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	158	1			T2	4		T4	2		T36	4
read_ops[0x0b]	134	1			T9	2		T100	4		T224	2
read_ops[0x3b]	198	1			T68	2		T37	4		T96	4
read_ops[0x6b]	154	1			T5	2		T68	2		T74	2
read_ops[0xbb]	144	1			T9	4		T12	4		T96	2
read_ops[0xeb]	178	1			T2	2		T5	4		T9	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	8	52	86.67	8

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x0b]]	[auto[ReadAddrCrossOutOfMailbox]]	*	--	--	2
[read_ops[0xbb]]	[auto[ReadAddrCrossOutOfMailbox]]	*	--	--	2
[read_ops[0xeb]]	[auto[ReadAddrCrossOutOfMailbox] , auto[ReadAddrCrossAllMailbox]]	*	--	--	4

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T253	1		T175	1		T201	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T253	1		T175	1		T201	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	5	1			T249	1		T175	4		-	-
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	5	1			T249	1		T175	4		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T279	2		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T279	2		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T95	1		T279	1		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T95	1		T279	1		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	63	1			T2	2		T4	1		T36	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	63	1			T2	2		T4	1		T36	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T165	1		T93	2		T264	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T165	1		T93	2		T264	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T253	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T253	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T235	1		T253	2		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T235	1		T253	2		-	-
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	55	1			T9	1		T100	2		T224	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	55	1			T9	1		T100	2		T224	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T93	3		T254	2		T94	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T93	3		T254	2		T94	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T253	1		T278	3		-	-
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T253	1		T278	3		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T278	1		T234	2		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T278	1		T234	2		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T253	1		T175	2		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T253	1		T175	2		-	-
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	81	1			T68	1		T37	2		T96	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	81	1			T68	1		T37	2		T96	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T279	1		T116	3		T223	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T279	1		T116	3		T223	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T279	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T279	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T279	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T279	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T279	2		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T279	2		-	-		-	-
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	67	1			T5	1		T68	1		T74	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	67	1			T5	1		T68	1		T74	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	12	1			T279	1		T235	1		T332	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	12	1			T279	1		T235	1		T332	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T9	2		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T9	2		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T279	1		T280	1		T267	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T279	1		T280	1		T267	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	54	1			T12	2		T96	1		T74	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	54	1			T12	2		T96	1		T74	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T160	2		T332	2		T269	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T160	2		T332	2		T269	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T175	2		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T175	2		-	-		-	-
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	80	1			T2	1		T5	2		T9	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	80	1			T2	1		T5	2		T9	1