Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	291140	1			T2	1		T3	1		T7	1
all_pins[1]	291140	1			T2	1		T3	1		T7	1
all_pins[2]	291140	1			T2	1		T3	1		T7	1
all_pins[3]	291140	1			T2	1		T3	1		T7	1
all_pins[4]	291140	1			T2	1		T3	1		T7	1
all_pins[5]	291140	1			T2	1		T3	1		T7	1
all_pins[6]	291140	1			T2	1		T3	1		T7	1
all_pins[7]	291140	1			T2	1		T3	1		T7	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2328144	1			T2	8		T3	8		T7	8
values[0x1]	976	1			T18	16		T20	20		T22	15
transitions[0x0=>0x1]	720	1			T18	13		T20	15		T22	12
transitions[0x1=>0x0]	732	1			T18	13		T20	15		T22	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	291010	1			T2	1		T3	1		T7	1
all_pins[0]	values[0x1]	130	1			T18	3		T20	2		T22	3
all_pins[0]	transitions[0x0=>0x1]	91	1			T18	3		T20	2		T22	3
all_pins[0]	transitions[0x1=>0x0]	92	1			T20	2		T22	1		T345	3
all_pins[1]	values[0x0]	291009	1			T2	1		T3	1		T7	1
all_pins[1]	values[0x1]	131	1			T20	2		T22	1		T345	5
all_pins[1]	transitions[0x0=>0x1]	105	1			T20	1		T22	1		T345	2
all_pins[1]	transitions[0x1=>0x0]	93	1			T18	3		T20	8		T22	1
all_pins[2]	values[0x0]	291021	1			T2	1		T3	1		T7	1
all_pins[2]	values[0x1]	119	1			T18	3		T20	9		T22	1
all_pins[2]	transitions[0x0=>0x1]	90	1			T18	3		T20	7		T22	1
all_pins[2]	transitions[0x1=>0x0]	89	1			T20	2		T22	1		T345	3
all_pins[3]	values[0x0]	291022	1			T2	1		T3	1		T7	1
all_pins[3]	values[0x1]	118	1			T20	4		T22	1		T345	5
all_pins[3]	transitions[0x0=>0x1]	96	1			T20	3		T22	1		T345	5
all_pins[3]	transitions[0x1=>0x0]	86	1			T18	3		T22	3		T345	3
all_pins[4]	values[0x0]	291032	1			T2	1		T3	1		T7	1
all_pins[4]	values[0x1]	108	1			T18	3		T20	1		T22	3
all_pins[4]	transitions[0x0=>0x1]	81	1			T18	2		T20	1		T22	2
all_pins[4]	transitions[0x1=>0x0]	95	1			T18	2		T22	2		T345	2
all_pins[5]	values[0x0]	291018	1			T2	1		T3	1		T7	1
all_pins[5]	values[0x1]	122	1			T18	3		T22	3		T345	3
all_pins[5]	transitions[0x0=>0x1]	93	1			T18	2		T22	2		T345	3
all_pins[5]	transitions[0x1=>0x0]	91	1			T22	1		T345	3		T346	3
all_pins[6]	values[0x0]	291020	1			T2	1		T3	1		T7	1
all_pins[6]	values[0x1]	120	1			T18	1		T22	2		T345	3
all_pins[6]	transitions[0x0=>0x1]	81	1			T18	1		T22	2		T345	3
all_pins[6]	transitions[0x1=>0x0]	89	1			T18	3		T20	2		T22	1
all_pins[7]	values[0x0]	291012	1			T2	1		T3	1		T7	1
all_pins[7]	values[0x1]	128	1			T18	3		T20	2		T22	1
all_pins[7]	transitions[0x0=>0x1]	83	1			T18	2		T20	1		T345	3
all_pins[7]	transitions[0x1=>0x0]	97	1			T18	2		T20	1		T22	2