Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
59.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	59	69	53.91

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	59	69	53.91	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	342	1			T122	2		T73	20		T74	18
values[1]	358	1			T2	20		T166	2		T167	12
values[2]	418	1			T5	26		T12	12		T68	12
values[3]	414	1			T95	6		T168	4		T169	2
values[4]	434	1			T71	14		T81	12		T26	6
values[5]	500	1			T4	6		T9	8		T163	2
values[6]	384	1			T3	2		T8	20		T96	8
values[7]	450	1			T11	2		T36	14		T67	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	198	1			T12	12		T67	2		T73	20
values[1]	398	1			T8	20		T95	6		T26	6
values[2]	342	1			T5	26		T68	12		T100	16
values[3]	430	1			T9	8		T81	12		T163	2
values[4]	564	1			T3	2		T64	22		T170	36
values[5]	478	1			T36	14		T72	18		T122	2
values[6]	460	1			T2	20		T4	6		T71	14
values[7]	430	1			T11	2		T166	2		T171	8

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3270

1

T2

20

T3

2

T4

6

auto[1]

30

1

T64

4

T65

4

T69

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	59	69	53.91	59

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[2]]	*	--	--	8
[auto[1]]	[values[6]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[1]]	0	1	1
[auto[0]]	[values[1]]	[values[0]]	0	1	1
[auto[0]]	[values[2]]	[values[7]]	0	1	1
[auto[0]]	[values[5]]	[values[1]]	0	1	1
[auto[1]]	[values[0]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[0]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[1]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[1]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5
[auto[1]]	[values[3]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[3]]	[values[4] , values[5] , values[6] , values[7]]	--	--	4
[auto[1]]	[values[4]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[4]]	[values[4]]	0	1	1
[auto[1]]	[values[4]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[5]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	7
[auto[1]]	[values[7]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[7]]	[values[6] , values[7]]	--	--	2

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	22	1			T73	20		T90	2		-	-
auto[0]	values[0]	values[2]	66	1			T172	12		T173	26		T174	24
auto[0]	values[0]	values[3]	48	1			T175	20		T176	6		T177	22
auto[0]	values[0]	values[4]	42	1			T162	14		T178	10		T179	6
auto[0]	values[0]	values[5]	80	1			T122	2		T74	18		T180	4
auto[0]	values[0]	values[6]	40	1			T181	4		T182	26		T183	10
auto[0]	values[0]	values[7]	38	1			T171	8		T184	30		-	-
auto[0]	values[1]	values[1]	32	1			T185	20		T186	2		T187	10
auto[0]	values[1]	values[2]	66	1			T188	14		T69	28		T39	6
auto[0]	values[1]	values[3]	56	1			T114	6		T189	32		T190	12
auto[0]	values[1]	values[4]	24	1			T191	12		T192	12		-	-
auto[0]	values[1]	values[5]	40	1			T167	12		T86	12		T193	6
auto[0]	values[1]	values[6]	68	1			T2	20		T194	26		T195	22
auto[0]	values[1]	values[7]	70	1			T166	2		T97	20		T196	32
auto[0]	values[2]	values[0]	22	1			T12	12		T52	10		-	-
auto[0]	values[2]	values[1]	126	1			T197	36		T198	12		T199	2
auto[0]	values[2]	values[2]	48	1			T5	26		T68	12		T200	10
auto[0]	values[2]	values[3]	52	1			T85	18		T201	18		T202	4
auto[0]	values[2]	values[4]	80	1			T170	36		T203	32		T204	12
auto[0]	values[2]	values[5]	12	1			T205	2		T206	4		T207	6
auto[0]	values[2]	values[6]	78	1			T25	8		T208	14		T113	2
auto[0]	values[3]	values[0]	26	1			T209	14		T210	12		-	-
auto[0]	values[3]	values[1]	80	1			T95	6		T211	34		T212	28
auto[0]	values[3]	values[2]	18	1			T213	18		-	-		-	-
auto[0]	values[3]	values[3]	64	1			T169	2		T214	4		T78	16
auto[0]	values[3]	values[4]	88	1			T215	22		T216	16		T217	24
auto[0]	values[3]	values[5]	30	1			T218	30		-	-		-	-
auto[0]	values[3]	values[6]	36	1			T160	6		T219	12		T220	18
auto[0]	values[3]	values[7]	70	1			T168	4		T24	4		T221	6
auto[0]	values[4]	values[0]	42	1			T161	14		T222	8		T223	20
auto[0]	values[4]	values[1]	60	1			T26	6		T224	26		T225	8
auto[0]	values[4]	values[2]	16	1			T70	12		T165	4		-	-
auto[0]	values[4]	values[3]	52	1			T81	12		T226	2		T75	10
auto[0]	values[4]	values[4]	44	1			T227	26		T228	18		-	-
auto[0]	values[4]	values[5]	84	1			T65	30		T164	6		T229	2
auto[0]	values[4]	values[6]	56	1			T71	14		T230	16		T231	4
auto[0]	values[4]	values[7]	72	1			T232	26		T233	30		T234	6
auto[0]	values[5]	values[0]	36	1			T235	4		T236	18		T237	4
auto[0]	values[5]	values[2]	54	1			T46	10		T238	18		T239	26
auto[0]	values[5]	values[3]	56	1			T9	8		T163	2		T240	22
auto[0]	values[5]	values[4]	108	1			T93	22		T241	2		T242	34
auto[0]	values[5]	values[5]	94	1			T243	14		T244	20		T245	18
auto[0]	values[5]	values[6]	78	1			T4	6		T66	26		T246	26
auto[0]	values[5]	values[7]	68	1			T247	12		T76	20		T248	20
auto[0]	values[6]	values[0]	8	1			T249	2		T250	6		-	-
auto[0]	values[6]	values[1]	58	1			T8	20		T251	2		T252	14
auto[0]	values[6]	values[2]	18	1			T253	18		-	-		-	-
auto[0]	values[6]	values[3]	44	1			T96	8		T254	8		T255	4
auto[0]	values[6]	values[4]	76	1			T3	2		T256	14		T257	20
auto[0]	values[6]	values[5]	44	1			T258	8		T94	8		T259	26
auto[0]	values[6]	values[6]	62	1			T260	38		T261	18		T262	6
auto[0]	values[6]	values[7]	74	1			T263	20		T264	10		T265	18
auto[0]	values[7]	values[0]	42	1			T67	2		T266	6		T267	12
auto[0]	values[7]	values[1]	42	1			T268	26		T269	12		T270	4
auto[0]	values[7]	values[2]	54	1			T100	16		T271	8		T272	20
auto[0]	values[7]	values[3]	52	1			T92	4		T273	14		T274	2
auto[0]	values[7]	values[4]	96	1			T64	18		T38	26		T275	18
auto[0]	values[7]	values[5]	84	1			T36	14		T72	18		T276	8
auto[0]	values[7]	values[6]	42	1			T37	6		T277	16		T278	10
auto[0]	values[7]	values[7]	32	1			T11	2		T279	26		T280	2
auto[1]	values[0]	values[4]	2	1			T80	2		-	-		-	-
auto[1]	values[0]	values[5]	4	1			T77	4		-	-		-	-
auto[1]	values[1]	values[2]	2	1			T69	2		-	-		-	-
auto[1]	values[3]	values[3]	2	1			T78	2		-	-		-	-
auto[1]	values[4]	values[3]	4	1			T75	4		-	-		-	-
auto[1]	values[4]	values[5]	4	1			T65	4		-	-		-	-
auto[1]	values[5]	values[7]	6	1			T76	6		-	-		-	-
auto[1]	values[7]	values[4]	4	1			T64	4		-	-		-	-
auto[1]	values[7]	values[5]	2	1			T79	2		-	-		-	-