SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_flip_position | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_opcode | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 164 | 1 | T87 | 2 | T82 | 6 | T88 | 4 | ||||
auto[1] | 144 | 1 | T87 | 2 | T82 | 6 | T88 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
read_ops[0x03] | 44 | 1 | T82 | 5 | T89 | 1 | T282 | 2 | ||||
read_ops[0x0b] | 61 | 1 | T88 | 2 | T99 | 4 | T286 | 3 | ||||
read_ops[0x3b] | 59 | 1 | T82 | 6 | T88 | 3 | T99 | 1 | ||||
read_ops[0x6b] | 64 | 1 | T87 | 1 | T82 | 1 | T88 | 2 | ||||
read_ops[0xbb] | 48 | 1 | T89 | 1 | T282 | 1 | T286 | 3 | ||||
read_ops[0xeb] | 32 | 1 | T87 | 3 | T298 | 2 | T293 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |