Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1442

1

T7

33

T13

9

T14

4

auto[1]

1450

1

T7

24

T13

23

T14

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

749

1

T13

30

T16

29

T17

23

auto[1]

2143

1

T7

57

T13

2

T14

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2625

1

T7

57

T13

20

T14

5

auto[1]

267

1

T13

12

T16

8

T17

7

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	568	1			T7	8		T13	6		T14	2
valid[1]	547	1			T7	18		T13	7		T14	1
valid[2]	612	1			T7	12		T13	6		T15	1
valid[3]	566	1			T7	6		T13	5		T16	9
valid[4]	599	1			T7	13		T13	8		T14	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	50	1			T16	3		T17	1		T57	1
auto[0]	auto[0]	valid[0]	auto[1]	211	1			T7	3		T14	2		T54	1
auto[0]	auto[0]	valid[1]	auto[0]	47	1			T13	4		T16	2		T17	2
auto[0]	auto[0]	valid[1]	auto[1]	188	1			T7	11		T14	1		T15	1
auto[0]	auto[0]	valid[2]	auto[0]	57	1			T16	2		T17	5		T103	1
auto[0]	auto[0]	valid[2]	auto[1]	198	1			T7	8		T15	1		T17	1
auto[0]	auto[0]	valid[3]	auto[0]	54	1			T13	1		T16	5		T17	3
auto[0]	auto[0]	valid[3]	auto[1]	228	1			T7	3		T17	2		T56	1
auto[0]	auto[0]	valid[4]	auto[0]	57	1			T13	2		T16	3		T17	1
auto[0]	auto[0]	valid[4]	auto[1]	206	1			T7	8		T14	1		T15	1
auto[0]	auto[1]	valid[0]	auto[0]	43	1			T13	5		T16	1		T17	1
auto[0]	auto[1]	valid[0]	auto[1]	205	1			T7	5		T83	2		T84	8
auto[0]	auto[1]	valid[1]	auto[0]	38	1			T13	1		T16	1		T17	1
auto[0]	auto[1]	valid[1]	auto[1]	222	1			T7	7		T13	1		T15	1
auto[0]	auto[1]	valid[2]	auto[0]	48	1			T13	2		T16	2		T17	1
auto[0]	auto[1]	valid[2]	auto[1]	254	1			T7	4		T13	1		T17	1
auto[0]	auto[1]	valid[3]	auto[0]	38	1			T16	2		T60	1		T384	3
auto[0]	auto[1]	valid[3]	auto[1]	193	1			T7	3		T56	2		T58	1
auto[0]	auto[1]	valid[4]	auto[0]	50	1			T13	3		T17	1		T103	1
auto[0]	auto[1]	valid[4]	auto[1]	238	1			T7	5		T14	1		T15	2
auto[1]	auto[0]	valid[0]	auto[0]	28	1			T13	1		T57	1		T374	1
auto[1]	auto[0]	valid[1]	auto[0]	29	1			T16	1		T17	1		T60	1
auto[1]	auto[0]	valid[2]	auto[0]	29	1			T16	1		T17	3		T57	1
auto[1]	auto[0]	valid[3]	auto[0]	32	1			T16	2		T17	1		T103	1
auto[1]	auto[0]	valid[4]	auto[0]	28	1			T13	1		T16	1		T60	1
auto[1]	auto[1]	valid[0]	auto[0]	31	1			T16	1		T60	1		T103	1
auto[1]	auto[1]	valid[1]	auto[0]	23	1			T13	1		T60	1		T103	2
auto[1]	auto[1]	valid[2]	auto[0]	26	1			T13	3		T16	1		T17	1
auto[1]	auto[1]	valid[3]	auto[0]	21	1			T13	4		T17	1		T384	1
auto[1]	auto[1]	valid[4]	auto[0]	20	1			T13	2		T16	1		T60	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal