Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18160

1

T13

534

T16

643

T17

532

auto[1]

20786

1

T7

529

T13

76

T14

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32204

1

T7

529

T13

396

T14

5

auto[1]

6742

1

T13

214

T16

205

T17

225

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	20334	1			T7	274		T13	314		T14	5
others[1]	3124	1			T7	36		T13	54		T16	55
others[2]	3266	1			T7	45		T13	48		T16	53
others[3]	3729	1			T7	51		T13	59		T16	71
interest[1]	2094	1			T7	28		T13	43		T16	36
interest[4]	13531	1			T7	175		T13	218		T14	5
interest[64]	6399	1			T7	95		T13	92		T16	109

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5930	1			T13	158		T16	209		T17	164
auto[0]	auto[0]	others[1]	927	1			T13	34		T16	39		T17	23
auto[0]	auto[0]	others[2]	915	1			T13	26		T16	38		T17	24
auto[0]	auto[0]	others[3]	1110	1			T13	32		T16	51		T17	38
auto[0]	auto[0]	interest[1]	633	1			T13	20		T16	26		T17	21
auto[0]	auto[0]	interest[4]	3920	1			T13	104		T16	145		T17	104
auto[0]	auto[0]	interest[64]	1903	1			T13	50		T16	75		T17	37
auto[0]	auto[1]	others[0]	10917	1			T7	274		T13	35		T14	5
auto[0]	auto[1]	others[1]	1649	1			T7	36		T13	10		T17	15
auto[0]	auto[1]	others[2]	1751	1			T7	45		T13	5		T17	10
auto[0]	auto[1]	others[3]	1999	1			T7	51		T13	5		T17	11
auto[0]	auto[1]	interest[1]	1098	1			T7	28		T13	12		T17	4
auto[0]	auto[1]	interest[4]	7306	1			T7	175		T13	22		T14	5
auto[0]	auto[1]	interest[64]	3372	1			T7	95		T13	9		T17	27
auto[1]	auto[0]	others[0]	3487	1			T13	121		T16	110		T17	109
auto[1]	auto[0]	others[1]	548	1			T13	10		T16	16		T17	13
auto[1]	auto[0]	others[2]	600	1			T13	17		T16	15		T17	23
auto[1]	auto[0]	others[3]	620	1			T13	22		T16	20		T17	20
auto[1]	auto[0]	interest[1]	363	1			T13	11		T16	10		T17	9
auto[1]	auto[0]	interest[4]	2305	1			T13	92		T16	75		T17	77
auto[1]	auto[0]	interest[64]	1124	1			T13	33		T16	34		T17	51

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal