Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	518	1			T18	11		T20	14		T22	7
all_values[1]	518	1			T18	11		T20	14		T22	7
all_values[2]	518	1			T18	11		T20	14		T22	7
all_values[3]	518	1			T18	11		T20	14		T22	7
all_values[4]	518	1			T18	11		T20	14		T22	7
all_values[5]	518	1			T18	11		T20	14		T22	7
all_values[6]	518	1			T18	11		T20	14		T22	7
all_values[7]	518	1			T18	11		T20	14		T22	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2216

1

T18

39

T20

60

T22

22

auto[1]

1928

1

T18

49

T20

52

T22

34

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1637

1

T18

46

T20

41

T22

22

auto[1]

2507

1

T18

42

T20

71

T22

34

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2354

1

T18

59

T20

63

T22

29

auto[1]

1790

1

T18

29

T20

49

T22

27

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	107	1			T18	3		T20	4		T345	1
all_values[0]	auto[0]	auto[0]	auto[1]	61	1			T18	1		T20	3		T345	3
all_values[0]	auto[0]	auto[1]	auto[0]	73	1			T18	2		T22	2		T345	2
all_values[0]	auto[0]	auto[1]	auto[1]	52	1			T18	2		T20	1		T22	1
all_values[0]	auto[1]	auto[0]	auto[1]	120	1			T18	2		T20	3		T22	2
all_values[0]	auto[1]	auto[1]	auto[1]	105	1			T18	1		T20	3		T22	2
all_values[1]	auto[0]	auto[0]	auto[0]	92	1			T18	3		T20	4		T345	2
all_values[1]	auto[0]	auto[0]	auto[1]	63	1			T18	1		T20	2		T22	1
all_values[1]	auto[0]	auto[1]	auto[0]	76	1			T18	3		T20	1		T22	1
all_values[1]	auto[0]	auto[1]	auto[1]	50	1			T22	1		T345	1		T346	4
all_values[1]	auto[1]	auto[0]	auto[1]	140	1			T18	4		T20	3		T22	3
all_values[1]	auto[1]	auto[1]	auto[1]	97	1			T20	4		T22	1		T345	9
all_values[2]	auto[0]	auto[0]	auto[0]	118	1			T18	1		T20	1		T22	2
all_values[2]	auto[0]	auto[0]	auto[1]	47	1			T20	1		T346	2		T347	1
all_values[2]	auto[0]	auto[1]	auto[0]	72	1			T18	4		T22	2		T345	2
all_values[2]	auto[0]	auto[1]	auto[1]	43	1			T18	3		T20	2		T345	3
all_values[2]	auto[1]	auto[0]	auto[1]	129	1			T18	1		T20	2		T22	2
all_values[2]	auto[1]	auto[1]	auto[1]	109	1			T18	2		T20	8		T22	1
all_values[3]	auto[0]	auto[0]	auto[0]	98	1			T18	2		T20	3		T345	4
all_values[3]	auto[0]	auto[0]	auto[1]	44	1			T18	2		T20	1		T22	1
all_values[3]	auto[0]	auto[1]	auto[0]	116	1			T18	5		T20	1		T22	3
all_values[3]	auto[0]	auto[1]	auto[1]	49	1			T20	1		T345	4		T346	1
all_values[3]	auto[1]	auto[0]	auto[1]	105	1			T18	2		T20	3		T22	2
all_values[3]	auto[1]	auto[1]	auto[1]	106	1			T20	5		T22	1		T345	2
all_values[4]	auto[0]	auto[0]	auto[0]	118	1			T18	2		T345	7		T346	6
all_values[4]	auto[0]	auto[0]	auto[1]	40	1			T18	1		T20	1		T345	1
all_values[4]	auto[0]	auto[1]	auto[0]	117	1			T18	3		T20	9		T22	2
all_values[4]	auto[0]	auto[1]	auto[1]	46	1			T18	1		T20	1		T22	2
all_values[4]	auto[1]	auto[0]	auto[1]	98	1			T20	1		T22	2		T345	4
all_values[4]	auto[1]	auto[1]	auto[1]	99	1			T18	4		T20	2		T22	1
all_values[5]	auto[0]	auto[0]	auto[0]	150	1			T18	3		T20	3		T345	6
all_values[5]	auto[0]	auto[1]	auto[0]	145	1			T18	4		T20	6		T22	2
all_values[5]	auto[1]	auto[0]	auto[1]	118	1			T18	2		T20	5		T22	2
all_values[5]	auto[1]	auto[1]	auto[1]	105	1			T18	2		T22	3		T345	1
all_values[6]	auto[0]	auto[0]	auto[0]	91	1			T18	1		T20	3		T345	2
all_values[6]	auto[0]	auto[0]	auto[1]	62	1			T18	1		T20	4		T22	1
all_values[6]	auto[0]	auto[1]	auto[0]	82	1			T18	5		T20	2		T22	3
all_values[6]	auto[0]	auto[1]	auto[1]	56	1			T345	1		T346	1		T347	2
all_values[6]	auto[1]	auto[0]	auto[1]	130	1			T18	2		T20	3		T22	1
all_values[6]	auto[1]	auto[1]	auto[1]	97	1			T18	2		T20	2		T22	2
all_values[7]	auto[0]	auto[0]	auto[0]	105	1			T18	2		T20	3		T22	2
all_values[7]	auto[0]	auto[0]	auto[1]	54	1			T20	4		T345	1		T346	4
all_values[7]	auto[0]	auto[1]	auto[0]	77	1			T18	3		T20	1		T22	3
all_values[7]	auto[0]	auto[1]	auto[1]	50	1			T18	1		T20	1		T345	2
all_values[7]	auto[1]	auto[0]	auto[1]	126	1			T18	3		T20	3		T22	1
all_values[7]	auto[1]	auto[1]	auto[1]	106	1			T18	2		T20	2		T22	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal