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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.06 97.56 92.92 98.61 80.85 95.95 90.92 87.64


Total test records in report: 861
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T145 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3464857041 Apr 15 12:26:49 PM PDT 24 Apr 15 12:26:51 PM PDT 24 63510238 ps
T350 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2040449379 Apr 15 12:27:19 PM PDT 24 Apr 15 12:27:39 PM PDT 24 1679308268 ps
T769 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3529017829 Apr 15 12:26:44 PM PDT 24 Apr 15 12:26:45 PM PDT 24 16640975 ps
T770 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.978253241 Apr 15 12:27:07 PM PDT 24 Apr 15 12:27:11 PM PDT 24 681793170 ps
T771 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4248040042 Apr 15 12:26:44 PM PDT 24 Apr 15 12:26:48 PM PDT 24 59672134 ps
T772 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4174184958 Apr 15 12:27:33 PM PDT 24 Apr 15 12:27:35 PM PDT 24 14880778 ps
T127 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2332908159 Apr 15 12:27:24 PM PDT 24 Apr 15 12:27:28 PM PDT 24 130232894 ps
T773 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2223293766 Apr 15 12:27:19 PM PDT 24 Apr 15 12:27:23 PM PDT 24 41326973 ps
T774 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4240381927 Apr 15 12:27:22 PM PDT 24 Apr 15 12:27:26 PM PDT 24 141763943 ps
T775 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.462995615 Apr 15 12:27:04 PM PDT 24 Apr 15 12:27:07 PM PDT 24 82974359 ps
T776 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.77203992 Apr 15 12:27:32 PM PDT 24 Apr 15 12:27:34 PM PDT 24 36728413 ps
T777 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3553821362 Apr 15 12:27:25 PM PDT 24 Apr 15 12:27:27 PM PDT 24 16064151 ps
T778 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2268636866 Apr 15 12:26:54 PM PDT 24 Apr 15 12:27:12 PM PDT 24 16575259722 ps
T779 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1536712116 Apr 15 12:27:21 PM PDT 24 Apr 15 12:27:24 PM PDT 24 162823584 ps
T128 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.929749796 Apr 15 12:27:16 PM PDT 24 Apr 15 12:27:21 PM PDT 24 155772747 ps
T780 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.750105699 Apr 15 12:27:21 PM PDT 24 Apr 15 12:27:23 PM PDT 24 14579240 ps
T781 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.510350341 Apr 15 12:26:50 PM PDT 24 Apr 15 12:26:52 PM PDT 24 17456142 ps
T782 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2580925623 Apr 15 12:27:09 PM PDT 24 Apr 15 12:27:11 PM PDT 24 67536386 ps
T143 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.385843849 Apr 15 12:26:51 PM PDT 24 Apr 15 12:27:25 PM PDT 24 524619604 ps
T783 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.58687642 Apr 15 12:27:10 PM PDT 24 Apr 15 12:27:12 PM PDT 24 117080756 ps
T784 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4263523118 Apr 15 12:27:07 PM PDT 24 Apr 15 12:27:10 PM PDT 24 219769455 ps
T146 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3354744659 Apr 15 12:26:47 PM PDT 24 Apr 15 12:26:49 PM PDT 24 133618798 ps
T785 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1984950162 Apr 15 12:26:42 PM PDT 24 Apr 15 12:26:57 PM PDT 24 2761283829 ps
T786 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.990147101 Apr 15 12:27:25 PM PDT 24 Apr 15 12:27:26 PM PDT 24 60980652 ps
T144 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1138471753 Apr 15 12:27:00 PM PDT 24 Apr 15 12:27:02 PM PDT 24 34252253 ps
T353 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3662790757 Apr 15 12:27:11 PM PDT 24 Apr 15 12:27:25 PM PDT 24 765417153 ps
T787 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1995662504 Apr 15 12:27:16 PM PDT 24 Apr 15 12:27:20 PM PDT 24 228147615 ps
T788 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3243727943 Apr 15 12:27:07 PM PDT 24 Apr 15 12:27:10 PM PDT 24 604785165 ps
T789 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.233779198 Apr 15 12:27:09 PM PDT 24 Apr 15 12:27:12 PM PDT 24 277663960 ps
T147 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4210694246 Apr 15 12:27:00 PM PDT 24 Apr 15 12:27:02 PM PDT 24 35544701 ps
T790 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1930682282 Apr 15 12:27:21 PM PDT 24 Apr 15 12:27:24 PM PDT 24 65486445 ps
T130 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4098803696 Apr 15 12:27:03 PM PDT 24 Apr 15 12:27:06 PM PDT 24 50284781 ps
T791 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1457506509 Apr 15 12:27:15 PM PDT 24 Apr 15 12:27:19 PM PDT 24 160750112 ps
T792 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3559177221 Apr 15 12:27:06 PM PDT 24 Apr 15 12:27:08 PM PDT 24 72531183 ps
T793 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.508144188 Apr 15 12:26:53 PM PDT 24 Apr 15 12:27:33 PM PDT 24 3685507161 ps
T794 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3833762277 Apr 15 12:27:17 PM PDT 24 Apr 15 12:27:19 PM PDT 24 19116840 ps
T795 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2284851778 Apr 15 12:27:01 PM PDT 24 Apr 15 12:27:03 PM PDT 24 104762143 ps
T796 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1187112934 Apr 15 12:27:14 PM PDT 24 Apr 15 12:27:17 PM PDT 24 78997944 ps
T797 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3836041755 Apr 15 12:27:20 PM PDT 24 Apr 15 12:27:21 PM PDT 24 16468860 ps
T798 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1940904672 Apr 15 12:26:49 PM PDT 24 Apr 15 12:26:50 PM PDT 24 44412951 ps
T799 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2633862280 Apr 15 12:27:07 PM PDT 24 Apr 15 12:27:08 PM PDT 24 20123404 ps
T800 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1625512741 Apr 15 12:27:09 PM PDT 24 Apr 15 12:27:12 PM PDT 24 48662216 ps
T801 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3940950240 Apr 15 12:26:52 PM PDT 24 Apr 15 12:26:56 PM PDT 24 92909612 ps
T802 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3458478993 Apr 15 12:26:59 PM PDT 24 Apr 15 12:27:15 PM PDT 24 216141924 ps
T803 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3002353434 Apr 15 12:26:53 PM PDT 24 Apr 15 12:26:54 PM PDT 24 17024117 ps
T101 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3280534479 Apr 15 12:26:44 PM PDT 24 Apr 15 12:26:46 PM PDT 24 42787999 ps
T804 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.814126163 Apr 15 12:26:50 PM PDT 24 Apr 15 12:26:52 PM PDT 24 12365264 ps
T805 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.237796919 Apr 15 12:27:11 PM PDT 24 Apr 15 12:27:14 PM PDT 24 904980515 ps
T806 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4019268082 Apr 15 12:27:33 PM PDT 24 Apr 15 12:27:35 PM PDT 24 35985217 ps
T348 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1496083159 Apr 15 12:27:00 PM PDT 24 Apr 15 12:27:04 PM PDT 24 388358954 ps
T807 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2465535914 Apr 15 12:27:24 PM PDT 24 Apr 15 12:27:25 PM PDT 24 20946546 ps
T808 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1244817946 Apr 15 12:26:43 PM PDT 24 Apr 15 12:26:47 PM PDT 24 520300838 ps
T809 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2912561111 Apr 15 12:26:41 PM PDT 24 Apr 15 12:26:44 PM PDT 24 119207951 ps
T810 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3776766291 Apr 15 12:26:43 PM PDT 24 Apr 15 12:26:47 PM PDT 24 107598195 ps
T148 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3316105136 Apr 15 12:26:43 PM PDT 24 Apr 15 12:27:22 PM PDT 24 10829498669 ps
T811 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1521398823 Apr 15 12:27:20 PM PDT 24 Apr 15 12:27:22 PM PDT 24 50175571 ps
T102 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.271608731 Apr 15 12:26:59 PM PDT 24 Apr 15 12:27:01 PM PDT 24 83093719 ps
T812 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2851038702 Apr 15 12:27:11 PM PDT 24 Apr 15 12:27:12 PM PDT 24 48272438 ps
T813 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1661090561 Apr 15 12:27:18 PM PDT 24 Apr 15 12:27:20 PM PDT 24 49578506 ps
T814 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.122167624 Apr 15 12:26:54 PM PDT 24 Apr 15 12:26:55 PM PDT 24 130270428 ps
T815 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2599155235 Apr 15 12:27:03 PM PDT 24 Apr 15 12:27:06 PM PDT 24 111479893 ps
T816 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.376540098 Apr 15 12:27:18 PM PDT 24 Apr 15 12:27:21 PM PDT 24 823373704 ps
T356 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1463213124 Apr 15 12:27:20 PM PDT 24 Apr 15 12:27:35 PM PDT 24 2451665628 ps
T817 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.355970716 Apr 15 12:27:21 PM PDT 24 Apr 15 12:27:24 PM PDT 24 68554273 ps
T818 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2645414004 Apr 15 12:27:18 PM PDT 24 Apr 15 12:27:22 PM PDT 24 169517388 ps
T149 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4270828292 Apr 15 12:26:50 PM PDT 24 Apr 15 12:27:05 PM PDT 24 12017446656 ps
T819 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3444309789 Apr 15 12:27:20 PM PDT 24 Apr 15 12:27:23 PM PDT 24 27695347 ps
T820 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3334907167 Apr 15 12:26:43 PM PDT 24 Apr 15 12:27:06 PM PDT 24 375877180 ps
T821 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4283765015 Apr 15 12:26:49 PM PDT 24 Apr 15 12:26:53 PM PDT 24 257594845 ps
T822 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2051779080 Apr 15 12:27:11 PM PDT 24 Apr 15 12:27:13 PM PDT 24 72413333 ps
T823 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3582008195 Apr 15 12:27:11 PM PDT 24 Apr 15 12:27:12 PM PDT 24 25887142 ps
T824 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2478945602 Apr 15 12:27:16 PM PDT 24 Apr 15 12:27:18 PM PDT 24 102884531 ps
T825 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4046155333 Apr 15 12:26:46 PM PDT 24 Apr 15 12:26:47 PM PDT 24 17352552 ps
T826 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3553314905 Apr 15 12:27:17 PM PDT 24 Apr 15 12:27:18 PM PDT 24 52437788 ps
T827 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2772294974 Apr 15 12:27:05 PM PDT 24 Apr 15 12:27:09 PM PDT 24 97827579 ps
T828 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3002574222 Apr 15 12:27:03 PM PDT 24 Apr 15 12:27:15 PM PDT 24 190678147 ps
T829 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2274207774 Apr 15 12:27:24 PM PDT 24 Apr 15 12:27:26 PM PDT 24 12909077 ps
T830 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3441847637 Apr 15 12:27:20 PM PDT 24 Apr 15 12:27:22 PM PDT 24 30679988 ps
T831 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1542503812 Apr 15 12:27:04 PM PDT 24 Apr 15 12:27:05 PM PDT 24 15911843 ps
T832 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1532071657 Apr 15 12:27:32 PM PDT 24 Apr 15 12:27:34 PM PDT 24 43726614 ps
T833 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1695378964 Apr 15 12:27:20 PM PDT 24 Apr 15 12:27:23 PM PDT 24 84213648 ps
T834 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4189229880 Apr 15 12:27:23 PM PDT 24 Apr 15 12:27:26 PM PDT 24 494362252 ps
T835 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2897369196 Apr 15 12:27:19 PM PDT 24 Apr 15 12:27:27 PM PDT 24 786929645 ps
T836 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.565014462 Apr 15 12:27:19 PM PDT 24 Apr 15 12:27:20 PM PDT 24 14551832 ps
T837 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2479201476 Apr 15 12:27:13 PM PDT 24 Apr 15 12:27:14 PM PDT 24 14211987 ps
T354 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1102185761 Apr 15 12:27:14 PM PDT 24 Apr 15 12:27:34 PM PDT 24 3212702245 ps
T838 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2971747035 Apr 15 12:27:12 PM PDT 24 Apr 15 12:27:16 PM PDT 24 182017222 ps
T839 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.520376037 Apr 15 12:27:23 PM PDT 24 Apr 15 12:27:26 PM PDT 24 564576034 ps
T840 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1931926800 Apr 15 12:27:27 PM PDT 24 Apr 15 12:27:28 PM PDT 24 12444544 ps
T841 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1290282346 Apr 15 12:26:50 PM PDT 24 Apr 15 12:26:51 PM PDT 24 12136139 ps
T842 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1672019349 Apr 15 12:27:04 PM PDT 24 Apr 15 12:27:06 PM PDT 24 35697253 ps
T843 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.741296469 Apr 15 12:26:44 PM PDT 24 Apr 15 12:26:52 PM PDT 24 1431099142 ps
T352 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3751741519 Apr 15 12:27:00 PM PDT 24 Apr 15 12:27:15 PM PDT 24 1293712564 ps
T844 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.192550040 Apr 15 12:26:46 PM PDT 24 Apr 15 12:26:49 PM PDT 24 181130611 ps
T845 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3339097282 Apr 15 12:27:14 PM PDT 24 Apr 15 12:27:18 PM PDT 24 2892153871 ps
T846 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2286794888 Apr 15 12:27:06 PM PDT 24 Apr 15 12:27:08 PM PDT 24 31042206 ps
T847 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2108803226 Apr 15 12:26:42 PM PDT 24 Apr 15 12:26:43 PM PDT 24 12329714 ps
T848 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2024318538 Apr 15 12:27:18 PM PDT 24 Apr 15 12:27:43 PM PDT 24 832935185 ps
T849 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2681359147 Apr 15 12:27:25 PM PDT 24 Apr 15 12:27:28 PM PDT 24 124460984 ps
T850 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1891449226 Apr 15 12:27:14 PM PDT 24 Apr 15 12:27:15 PM PDT 24 10943501 ps
T851 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3805881040 Apr 15 12:27:28 PM PDT 24 Apr 15 12:27:35 PM PDT 24 1069857357 ps
T852 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1326400782 Apr 15 12:26:53 PM PDT 24 Apr 15 12:26:54 PM PDT 24 44224794 ps
T853 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3363073104 Apr 15 12:27:04 PM PDT 24 Apr 15 12:27:05 PM PDT 24 18005499 ps
T854 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2597690151 Apr 15 12:26:44 PM PDT 24 Apr 15 12:26:48 PM PDT 24 205415325 ps
T855 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3952845331 Apr 15 12:26:57 PM PDT 24 Apr 15 12:26:59 PM PDT 24 25719300 ps
T856 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.757226617 Apr 15 12:27:33 PM PDT 24 Apr 15 12:27:35 PM PDT 24 14043057 ps
T857 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1882136596 Apr 15 12:26:45 PM PDT 24 Apr 15 12:26:46 PM PDT 24 17086949 ps
T858 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1716809671 Apr 15 12:27:27 PM PDT 24 Apr 15 12:27:28 PM PDT 24 14839454 ps
T859 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3405738584 Apr 15 12:27:14 PM PDT 24 Apr 15 12:27:27 PM PDT 24 219080350 ps
T860 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4186424208 Apr 15 12:26:50 PM PDT 24 Apr 15 12:26:53 PM PDT 24 103767056 ps
T861 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3672986338 Apr 15 12:26:43 PM PDT 24 Apr 15 12:26:45 PM PDT 24 41558695 ps

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.573565071
Short name T2
Test name
Test status
Simulation time 497096568 ps
CPU time 6.36 seconds
Started Apr 15 01:23:45 PM PDT 24
Finished Apr 15 01:23:52 PM PDT 24
Peak memory 232492 kb
Host smart-b9da7e3f-4445-4067-a3ed-b9c443bfd490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573565071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.573565071
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1133918296
Short name T13
Test name
Test status
Simulation time 16268731156 ps
CPU time 60.25 seconds
Started Apr 15 01:22:44 PM PDT 24
Finished Apr 15 01:23:45 PM PDT 24
Peak memory 216636 kb
Host smart-be970460-0bcc-4ca2-8089-6e3c8aff79d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133918296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1133918296
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_upload.3281721144
Short name T170
Test name
Test status
Simulation time 21807422775 ps
CPU time 60.6 seconds
Started Apr 15 01:26:07 PM PDT 24
Finished Apr 15 01:27:08 PM PDT 24
Peak memory 233152 kb
Host smart-625e2f72-6ba0-4702-94b9-11acbc84ffcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281721144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3281721144
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2683229705
Short name T242
Test name
Test status
Simulation time 60830979462 ps
CPU time 163.59 seconds
Started Apr 15 01:25:57 PM PDT 24
Finished Apr 15 01:28:41 PM PDT 24
Peak memory 240680 kb
Host smart-231970a7-dcc4-4e43-b550-5c84bd7e5209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683229705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2683229705
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1924858247
Short name T118
Test name
Test status
Simulation time 686252607 ps
CPU time 15.15 seconds
Started Apr 15 12:26:53 PM PDT 24
Finished Apr 15 12:27:08 PM PDT 24
Peak memory 215288 kb
Host smart-92cdfb19-87c6-4223-9a91-fdd4e7f93ab4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924858247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1924858247
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1434959529
Short name T20
Test name
Test status
Simulation time 35087680 ps
CPU time 0.92 seconds
Started Apr 15 01:22:55 PM PDT 24
Finished Apr 15 01:22:56 PM PDT 24
Peak memory 207060 kb
Host smart-97055d5c-1c78-4d56-8517-cd80140cf969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434959529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1434959529
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.994387929
Short name T386
Test name
Test status
Simulation time 30220760408 ps
CPU time 45.31 seconds
Started Apr 15 01:30:44 PM PDT 24
Finished Apr 15 01:31:29 PM PDT 24
Peak memory 216644 kb
Host smart-7ff54167-87a8-4a28-acd5-28ce45b9279c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994387929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.994387929
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.708018727
Short name T8
Test name
Test status
Simulation time 2544033741 ps
CPU time 9.04 seconds
Started Apr 15 01:25:23 PM PDT 24
Finished Apr 15 01:25:32 PM PDT 24
Peak memory 218880 kb
Host smart-70fdbc85-5b5b-4c41-9ca2-af3a7f885056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708018727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.708018727
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_upload.2190817969
Short name T66
Test name
Test status
Simulation time 3125443227 ps
CPU time 12.56 seconds
Started Apr 15 01:27:37 PM PDT 24
Finished Apr 15 01:27:50 PM PDT 24
Peak memory 217952 kb
Host smart-d6ade2a5-41bd-41dc-bd84-d9c9b848add3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190817969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2190817969
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.270762867
Short name T17
Test name
Test status
Simulation time 11442234646 ps
CPU time 31.97 seconds
Started Apr 15 01:23:21 PM PDT 24
Finished Apr 15 01:23:53 PM PDT 24
Peak memory 216528 kb
Host smart-605e8074-2902-425a-8adf-cf1b4e554c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270762867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.270762867
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.4084048249
Short name T35
Test name
Test status
Simulation time 16009285 ps
CPU time 0.75 seconds
Started Apr 15 01:22:19 PM PDT 24
Finished Apr 15 01:22:20 PM PDT 24
Peak memory 216412 kb
Host smart-365f69e4-c107-4c68-ae8e-504889828cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084048249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.4084048249
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2130170892
Short name T9
Test name
Test status
Simulation time 139123010335 ps
CPU time 163.25 seconds
Started Apr 15 01:28:32 PM PDT 24
Finished Apr 15 01:31:15 PM PDT 24
Peak memory 232228 kb
Host smart-2d54e0e9-3bc6-4562-8d59-ee9dce8e6c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130170892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2130170892
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3710966993
Short name T112
Test name
Test status
Simulation time 2115798928 ps
CPU time 9.88 seconds
Started Apr 15 01:31:12 PM PDT 24
Finished Apr 15 01:31:23 PM PDT 24
Peak memory 223532 kb
Host smart-bd6cb52c-81f9-410c-8e27-1983e8f90927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710966993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3710966993
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3850520132
Short name T390
Test name
Test status
Simulation time 14402540710 ps
CPU time 37.56 seconds
Started Apr 15 01:24:00 PM PDT 24
Finished Apr 15 01:24:38 PM PDT 24
Peak memory 216656 kb
Host smart-4a63b2a9-83ca-48b4-88d8-941a69e2c17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850520132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3850520132
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.998304094
Short name T88
Test name
Test status
Simulation time 3039367686 ps
CPU time 20.42 seconds
Started Apr 15 01:28:31 PM PDT 24
Finished Apr 15 01:28:51 PM PDT 24
Peak memory 241236 kb
Host smart-51366029-e5ba-45a4-874b-a4c5875608dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998304094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.998304094
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1531515307
Short name T69
Test name
Test status
Simulation time 3463840634 ps
CPU time 14.37 seconds
Started Apr 15 01:22:31 PM PDT 24
Finished Apr 15 01:22:46 PM PDT 24
Peak memory 224744 kb
Host smart-4fc97d2c-3329-4e87-99f4-8cfc680a692d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531515307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1531515307
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3054918812
Short name T108
Test name
Test status
Simulation time 184452190 ps
CPU time 4.63 seconds
Started Apr 15 12:27:15 PM PDT 24
Finished Apr 15 12:27:20 PM PDT 24
Peak memory 215468 kb
Host smart-6e4083d9-d1ae-433b-962b-4137243154a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054918812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3054918812
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2175268226
Short name T40
Test name
Test status
Simulation time 81868450 ps
CPU time 1.1 seconds
Started Apr 15 01:22:29 PM PDT 24
Finished Apr 15 01:22:30 PM PDT 24
Peak memory 235536 kb
Host smart-93f66735-3479-45a9-bc28-fec98c2fe303
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175268226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2175268226
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3948764646
Short name T279
Test name
Test status
Simulation time 15173910967 ps
CPU time 119.38 seconds
Started Apr 15 01:29:35 PM PDT 24
Finished Apr 15 01:31:35 PM PDT 24
Peak memory 222328 kb
Host smart-c7137d60-bd68-4202-adcd-87d67656bffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948764646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3948764646
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3953047390
Short name T73
Test name
Test status
Simulation time 1690561908 ps
CPU time 12 seconds
Started Apr 15 01:28:16 PM PDT 24
Finished Apr 15 01:28:29 PM PDT 24
Peak memory 237744 kb
Host smart-3773e18c-03a6-4547-99b6-a75f068bb211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953047390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3953047390
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1744570566
Short name T224
Test name
Test status
Simulation time 14319932874 ps
CPU time 24.4 seconds
Started Apr 15 01:27:38 PM PDT 24
Finished Apr 15 01:28:03 PM PDT 24
Peak memory 230060 kb
Host smart-f05864b6-1943-4d2b-a01a-52ea15c552a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744570566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1744570566
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.685630998
Short name T137
Test name
Test status
Simulation time 1458519893 ps
CPU time 1.94 seconds
Started Apr 15 12:26:43 PM PDT 24
Finished Apr 15 12:26:46 PM PDT 24
Peak memory 215244 kb
Host smart-cc84fe52-12bc-4377-89ba-68d08c19d9a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685630998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.685630998
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/default/15.spi_device_upload.3356888428
Short name T182
Test name
Test status
Simulation time 1332434250 ps
CPU time 12.23 seconds
Started Apr 15 01:24:18 PM PDT 24
Finished Apr 15 01:24:30 PM PDT 24
Peak memory 224784 kb
Host smart-81416be3-d938-4323-8516-f45aa69d25e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356888428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3356888428
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.771180568
Short name T253
Test name
Test status
Simulation time 28774632035 ps
CPU time 134.27 seconds
Started Apr 15 01:22:33 PM PDT 24
Finished Apr 15 01:24:48 PM PDT 24
Peak memory 233992 kb
Host smart-8129f0b0-a1b9-418c-9979-77dc0c17967c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771180568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.771180568
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1308349658
Short name T156
Test name
Test status
Simulation time 274768752 ps
CPU time 0.91 seconds
Started Apr 15 01:23:13 PM PDT 24
Finished Apr 15 01:23:15 PM PDT 24
Peak memory 206908 kb
Host smart-9bf992e9-86fc-458b-885d-dfe928085e5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308349658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1308349658
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2699903518
Short name T65
Test name
Test status
Simulation time 1462955529 ps
CPU time 10.62 seconds
Started Apr 15 01:25:27 PM PDT 24
Finished Apr 15 01:25:38 PM PDT 24
Peak memory 226956 kb
Host smart-d0cc9c38-0809-4bfe-9945-b7a17a62f601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699903518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2699903518
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1648681651
Short name T12
Test name
Test status
Simulation time 11921967679 ps
CPU time 20.48 seconds
Started Apr 15 01:25:20 PM PDT 24
Finished Apr 15 01:25:41 PM PDT 24
Peak memory 232936 kb
Host smart-07b7babf-b49d-4d81-bbc9-249e517a68d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648681651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1648681651
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1458754369
Short name T63
Test name
Test status
Simulation time 30621238 ps
CPU time 1.07 seconds
Started Apr 15 01:22:26 PM PDT 24
Finished Apr 15 01:22:28 PM PDT 24
Peak memory 218224 kb
Host smart-61e2f5d0-effd-4839-980c-6ba25a0e5f11
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458754369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1458754369
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3790911918
Short name T215
Test name
Test status
Simulation time 26206594940 ps
CPU time 20.02 seconds
Started Apr 15 01:24:39 PM PDT 24
Finished Apr 15 01:24:59 PM PDT 24
Peak memory 227192 kb
Host smart-39e943ff-87dc-41d6-9da5-384830868c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790911918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3790911918
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3500040162
Short name T93
Test name
Test status
Simulation time 1597519806 ps
CPU time 16.24 seconds
Started Apr 15 01:25:00 PM PDT 24
Finished Apr 15 01:25:16 PM PDT 24
Peak memory 219588 kb
Host smart-3e733691-882e-49b5-8f96-b2a5cb1800e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500040162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3500040162
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1584806680
Short name T246
Test name
Test status
Simulation time 1519362436 ps
CPU time 6.39 seconds
Started Apr 15 01:25:56 PM PDT 24
Finished Apr 15 01:26:03 PM PDT 24
Peak memory 218736 kb
Host smart-70be1879-7093-4023-95bc-850a04318ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584806680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1584806680
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3837555552
Short name T103
Test name
Test status
Simulation time 4737192038 ps
CPU time 31.15 seconds
Started Apr 15 01:26:04 PM PDT 24
Finished Apr 15 01:26:36 PM PDT 24
Peak memory 221520 kb
Host smart-24af71ea-29ac-405d-b533-7beb1645dfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837555552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3837555552
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2772897556
Short name T385
Test name
Test status
Simulation time 6430292891 ps
CPU time 37.58 seconds
Started Apr 15 01:31:08 PM PDT 24
Finished Apr 15 01:31:46 PM PDT 24
Peak memory 216592 kb
Host smart-df0d4a8f-d427-4477-a569-c85e2a3b7737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772897556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2772897556
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3079860432
Short name T209
Test name
Test status
Simulation time 8207174755 ps
CPU time 7.6 seconds
Started Apr 15 01:22:30 PM PDT 24
Finished Apr 15 01:22:38 PM PDT 24
Peak memory 218652 kb
Host smart-1e3ee713-9fab-437b-bc36-04de8b4d08eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079860432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3079860432
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.181278811
Short name T74
Test name
Test status
Simulation time 19524454613 ps
CPU time 13.93 seconds
Started Apr 15 01:24:50 PM PDT 24
Finished Apr 15 01:25:04 PM PDT 24
Peak memory 223356 kb
Host smart-0182653a-5754-4d00-9d48-0cb5f0acdc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181278811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.181278811
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4288192860
Short name T343
Test name
Test status
Simulation time 1327471967 ps
CPU time 6.85 seconds
Started Apr 15 01:24:45 PM PDT 24
Finished Apr 15 01:24:52 PM PDT 24
Peak memory 223168 kb
Host smart-286baa08-5949-47fb-8e9e-3f6dfa78265b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288192860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.4288192860
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1937468660
Short name T245
Test name
Test status
Simulation time 9951247379 ps
CPU time 8.84 seconds
Started Apr 15 01:24:39 PM PDT 24
Finished Apr 15 01:24:48 PM PDT 24
Peak memory 223620 kb
Host smart-08a7dcf4-946a-4dc7-bbd3-ad1d9b6572a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937468660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1937468660
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2557650399
Short name T76
Test name
Test status
Simulation time 16662619256 ps
CPU time 20.95 seconds
Started Apr 15 01:25:49 PM PDT 24
Finished Apr 15 01:26:10 PM PDT 24
Peak memory 230840 kb
Host smart-0b562913-2738-4690-9842-4c5ff14a6c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557650399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2557650399
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.418803403
Short name T175
Test name
Test status
Simulation time 47106494164 ps
CPU time 92.13 seconds
Started Apr 15 01:27:05 PM PDT 24
Finished Apr 15 01:28:38 PM PDT 24
Peak memory 238100 kb
Host smart-9e086fe6-3e8c-4d05-ab59-f115f8b7c0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418803403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.418803403
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1629071601
Short name T283
Test name
Test status
Simulation time 1181240301 ps
CPU time 18.07 seconds
Started Apr 15 01:25:01 PM PDT 24
Finished Apr 15 01:25:20 PM PDT 24
Peak memory 241172 kb
Host smart-a49e8203-2430-4bbe-9d63-a510c8c44d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629071601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1629071601
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2958301116
Short name T75
Test name
Test status
Simulation time 1243856043 ps
CPU time 11.29 seconds
Started Apr 15 01:26:26 PM PDT 24
Finished Apr 15 01:26:38 PM PDT 24
Peak memory 238284 kb
Host smart-c4223794-0c58-4bff-a7ea-dbce15ed1871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958301116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2958301116
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3491659534
Short name T79
Test name
Test status
Simulation time 1700510695 ps
CPU time 10.7 seconds
Started Apr 15 01:30:32 PM PDT 24
Finished Apr 15 01:30:43 PM PDT 24
Peak memory 234084 kb
Host smart-d87d508c-eba3-4f6e-87c6-0f4cf3bf1086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491659534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3491659534
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_intercept.525203142
Short name T38
Test name
Test status
Simulation time 765157197 ps
CPU time 6.01 seconds
Started Apr 15 01:24:26 PM PDT 24
Finished Apr 15 01:24:32 PM PDT 24
Peak memory 232816 kb
Host smart-74dcf355-d318-4113-b81b-5ba841cc7bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525203142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.525203142
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2089281842
Short name T223
Test name
Test status
Simulation time 4671101762 ps
CPU time 40.93 seconds
Started Apr 15 01:28:44 PM PDT 24
Finished Apr 15 01:29:25 PM PDT 24
Peak memory 232692 kb
Host smart-0200d652-6ec0-4162-b41b-cc654f02d972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089281842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2089281842
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_intercept.760320504
Short name T86
Test name
Test status
Simulation time 4292934889 ps
CPU time 36.07 seconds
Started Apr 15 01:27:37 PM PDT 24
Finished Apr 15 01:28:13 PM PDT 24
Peak memory 223716 kb
Host smart-b326621f-559e-41d4-b1df-16d2da5b8e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760320504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.760320504
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1880644003
Short name T320
Test name
Test status
Simulation time 214431499 ps
CPU time 4.82 seconds
Started Apr 15 01:24:50 PM PDT 24
Finished Apr 15 01:24:56 PM PDT 24
Peak memory 233012 kb
Host smart-b89ad2c8-19ce-4ba1-86c1-d445e41a2565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880644003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1880644003
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.675423340
Short name T295
Test name
Test status
Simulation time 4497332032 ps
CPU time 34.34 seconds
Started Apr 15 01:22:51 PM PDT 24
Finished Apr 15 01:23:25 PM PDT 24
Peak memory 241216 kb
Host smart-47deaa2e-953b-4718-ab55-e820e804bd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675423340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.675423340
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1701857936
Short name T415
Test name
Test status
Simulation time 118280202 ps
CPU time 0.72 seconds
Started Apr 15 01:25:24 PM PDT 24
Finished Apr 15 01:25:25 PM PDT 24
Peak memory 205396 kb
Host smart-ef8f1a3f-51c1-425f-9de7-1ade62c03763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701857936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1701857936
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4219962562
Short name T123
Test name
Test status
Simulation time 669292389 ps
CPU time 4.6 seconds
Started Apr 15 12:27:20 PM PDT 24
Finished Apr 15 12:27:26 PM PDT 24
Peak memory 212580 kb
Host smart-fce0d10d-ec3f-4e0c-9df4-47e558588d3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219962562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
4219962562
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_intercept.54286731
Short name T96
Test name
Test status
Simulation time 3213558608 ps
CPU time 37.35 seconds
Started Apr 15 01:22:18 PM PDT 24
Finished Apr 15 01:22:55 PM PDT 24
Peak memory 224228 kb
Host smart-5ad74cee-5b07-431e-b38e-64fad9af66e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54286731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.54286731
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2571166795
Short name T278
Test name
Test status
Simulation time 33739874952 ps
CPU time 50.74 seconds
Started Apr 15 01:23:59 PM PDT 24
Finished Apr 15 01:24:50 PM PDT 24
Peak memory 224528 kb
Host smart-9f870a4f-e9b7-4f76-ae6b-6be176b6ad05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571166795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2571166795
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.583342421
Short name T325
Test name
Test status
Simulation time 215074313 ps
CPU time 3.51 seconds
Started Apr 15 01:25:00 PM PDT 24
Finished Apr 15 01:25:04 PM PDT 24
Peak memory 223344 kb
Host smart-6ccd89a7-3fbb-4fd6-9870-7fa4ef84a03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583342421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.583342421
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.914554281
Short name T398
Test name
Test status
Simulation time 21891115085 ps
CPU time 28.16 seconds
Started Apr 15 01:25:56 PM PDT 24
Finished Apr 15 01:26:25 PM PDT 24
Peak memory 216584 kb
Host smart-962e12b6-081e-44e8-a887-792e8290da00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914554281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.914554281
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1241086870
Short name T173
Test name
Test status
Simulation time 6155466717 ps
CPU time 7.59 seconds
Started Apr 15 01:26:15 PM PDT 24
Finished Apr 15 01:26:23 PM PDT 24
Peak memory 224268 kb
Host smart-06d81775-6030-41d6-a8df-66b7308e3807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241086870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1241086870
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1415918064
Short name T77
Test name
Test status
Simulation time 3910645886 ps
CPU time 16.82 seconds
Started Apr 15 01:23:27 PM PDT 24
Finished Apr 15 01:23:45 PM PDT 24
Peak memory 222112 kb
Host smart-62d93037-339e-4247-8bd4-771f264095e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415918064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1415918064
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1873809306
Short name T117
Test name
Test status
Simulation time 1834514409 ps
CPU time 8.57 seconds
Started Apr 15 12:27:14 PM PDT 24
Finished Apr 15 12:27:23 PM PDT 24
Peak memory 215876 kb
Host smart-1d49a223-9f80-487a-ad50-636c8790409e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873809306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1873809306
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3013448859
Short name T189
Test name
Test status
Simulation time 2112588032 ps
CPU time 14.88 seconds
Started Apr 15 01:23:44 PM PDT 24
Finished Apr 15 01:23:59 PM PDT 24
Peak memory 236212 kb
Host smart-4c4546b8-3f00-459d-bd43-1eaec717a625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013448859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3013448859
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1166128800
Short name T191
Test name
Test status
Simulation time 290830622 ps
CPU time 5.34 seconds
Started Apr 15 01:24:18 PM PDT 24
Finished Apr 15 01:24:24 PM PDT 24
Peak memory 222624 kb
Host smart-d1ba04bb-7dce-4d80-b918-c2fb7417103e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166128800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1166128800
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_upload.4123600312
Short name T256
Test name
Test status
Simulation time 1948585585 ps
CPU time 6.66 seconds
Started Apr 15 01:24:43 PM PDT 24
Finished Apr 15 01:24:50 PM PDT 24
Peak memory 232940 kb
Host smart-61a62df4-16e4-4ddf-bfdc-b1a73792ca8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123600312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.4123600312
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2064812359
Short name T97
Test name
Test status
Simulation time 422822953 ps
CPU time 7.06 seconds
Started Apr 15 01:25:16 PM PDT 24
Finished Apr 15 01:25:23 PM PDT 24
Peak memory 224368 kb
Host smart-71fd3d17-062c-4930-a081-da175644e02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064812359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2064812359
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1645980671
Short name T236
Test name
Test status
Simulation time 9071273102 ps
CPU time 11.95 seconds
Started Apr 15 01:25:29 PM PDT 24
Finished Apr 15 01:25:41 PM PDT 24
Peak memory 219752 kb
Host smart-4b9eac36-f47c-4343-8962-dbdd7ae19a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645980671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1645980671
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1463213124
Short name T356
Test name
Test status
Simulation time 2451665628 ps
CPU time 13.95 seconds
Started Apr 15 12:27:20 PM PDT 24
Finished Apr 15 12:27:35 PM PDT 24
Peak memory 215444 kb
Host smart-3df4bc7e-67de-49de-92e2-0328a13be2f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463213124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1463213124
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2286915772
Short name T362
Test name
Test status
Simulation time 1614344399 ps
CPU time 13.13 seconds
Started Apr 15 01:22:19 PM PDT 24
Finished Apr 15 01:22:32 PM PDT 24
Peak memory 236532 kb
Host smart-18d51f42-c300-4e7f-b453-2b38289fca13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286915772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2286915772
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.156054035
Short name T7
Test name
Test status
Simulation time 23088972300 ps
CPU time 16.31 seconds
Started Apr 15 01:23:52 PM PDT 24
Finished Apr 15 01:24:09 PM PDT 24
Peak memory 216568 kb
Host smart-6ab25683-13af-41a7-a9e3-274206d7dda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156054035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.156054035
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3257818907
Short name T211
Test name
Test status
Simulation time 1439549360 ps
CPU time 6.08 seconds
Started Apr 15 01:24:27 PM PDT 24
Finished Apr 15 01:24:34 PM PDT 24
Peak memory 216996 kb
Host smart-97e8fbb1-867d-4210-a9aa-6dc3364e71f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257818907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3257818907
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_intercept.575775869
Short name T324
Test name
Test status
Simulation time 7265104033 ps
CPU time 23.91 seconds
Started Apr 15 01:24:42 PM PDT 24
Finished Apr 15 01:25:06 PM PDT 24
Peak memory 222608 kb
Host smart-8c3f3b6c-1e69-469d-95fc-c315b1e6de14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575775869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.575775869
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.734064405
Short name T194
Test name
Test status
Simulation time 8650129007 ps
CPU time 22.62 seconds
Started Apr 15 01:25:08 PM PDT 24
Finished Apr 15 01:25:31 PM PDT 24
Peak memory 235704 kb
Host smart-9fc9688d-83a8-4c5a-af80-30aa26a4d268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734064405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.734064405
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1605472252
Short name T363
Test name
Test status
Simulation time 9212166641 ps
CPU time 33.83 seconds
Started Apr 15 01:25:31 PM PDT 24
Finished Apr 15 01:26:06 PM PDT 24
Peak memory 234128 kb
Host smart-3e85826f-581d-4bff-a84f-f6bc017db747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605472252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1605472252
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2177004685
Short name T94
Test name
Test status
Simulation time 2023337253 ps
CPU time 9.18 seconds
Started Apr 15 01:25:48 PM PDT 24
Finished Apr 15 01:25:58 PM PDT 24
Peak memory 223328 kb
Host smart-a6df7a08-c57c-4a75-8d2a-963e73df30c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177004685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2177004685
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3744332828
Short name T115
Test name
Test status
Simulation time 1092587654 ps
CPU time 4.08 seconds
Started Apr 15 01:26:14 PM PDT 24
Finished Apr 15 01:26:19 PM PDT 24
Peak memory 219348 kb
Host smart-9530c981-383d-4652-9d1c-e08e70e97454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744332828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3744332828
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_upload.3930275401
Short name T313
Test name
Test status
Simulation time 4652228669 ps
CPU time 10.03 seconds
Started Apr 15 01:26:42 PM PDT 24
Finished Apr 15 01:26:52 PM PDT 24
Peak memory 235208 kb
Host smart-655f6b37-a9d5-47a2-b91e-c46dde6a631b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930275401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3930275401
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1784526083
Short name T201
Test name
Test status
Simulation time 3903703932 ps
CPU time 32.61 seconds
Started Apr 15 01:28:20 PM PDT 24
Finished Apr 15 01:28:53 PM PDT 24
Peak memory 218912 kb
Host smart-3bbdcaa9-9a30-4834-bbfd-ee068714d7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784526083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1784526083
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3362225593
Short name T80
Test name
Test status
Simulation time 8554999517 ps
CPU time 19.02 seconds
Started Apr 15 01:30:13 PM PDT 24
Finished Apr 15 01:30:32 PM PDT 24
Peak memory 224792 kb
Host smart-49fb38c5-da90-4ed1-b0e8-f80df06fe4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362225593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3362225593
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3296841154
Short name T197
Test name
Test status
Simulation time 4467829868 ps
CPU time 14.15 seconds
Started Apr 15 01:23:23 PM PDT 24
Finished Apr 15 01:23:38 PM PDT 24
Peak memory 222672 kb
Host smart-e924b2aa-6673-4076-abbf-3aa463390365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296841154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3296841154
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3243703112
Short name T105
Test name
Test status
Simulation time 1827981109 ps
CPU time 26.92 seconds
Started Apr 15 01:25:07 PM PDT 24
Finished Apr 15 01:25:34 PM PDT 24
Peak memory 216696 kb
Host smart-b069de65-9107-44fe-a12d-9b87bf475284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243703112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3243703112
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.643840407
Short name T336
Test name
Test status
Simulation time 4153019142 ps
CPU time 13.14 seconds
Started Apr 15 01:23:38 PM PDT 24
Finished Apr 15 01:23:51 PM PDT 24
Peak memory 216876 kb
Host smart-a1afd396-5e83-4de0-a402-74f6ffc98691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643840407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.643840407
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3815836942
Short name T213
Test name
Test status
Simulation time 5635595647 ps
CPU time 25.78 seconds
Started Apr 15 01:24:09 PM PDT 24
Finished Apr 15 01:24:36 PM PDT 24
Peak memory 232160 kb
Host smart-bd978355-c3e6-437b-8914-b0903fbbcc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815836942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3815836942
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.319697653
Short name T228
Test name
Test status
Simulation time 6542600829 ps
CPU time 45.95 seconds
Started Apr 15 01:24:18 PM PDT 24
Finished Apr 15 01:25:04 PM PDT 24
Peak memory 249588 kb
Host smart-69a86ea4-3b8b-4a66-8ac8-1d1800400f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319697653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.319697653
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.407004145
Short name T334
Test name
Test status
Simulation time 2381017008 ps
CPU time 7.63 seconds
Started Apr 15 01:24:16 PM PDT 24
Finished Apr 15 01:24:24 PM PDT 24
Peak memory 221580 kb
Host smart-9fc37b53-8aa3-4009-8a25-44d5d41a4ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407004145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.407004145
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1044893225
Short name T372
Test name
Test status
Simulation time 4276355807 ps
CPU time 47.88 seconds
Started Apr 15 01:24:50 PM PDT 24
Finished Apr 15 01:25:38 PM PDT 24
Peak memory 253344 kb
Host smart-9692adb5-f417-4cd3-b718-5210f49f2198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044893225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1044893225
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.192855584
Short name T255
Test name
Test status
Simulation time 190274924 ps
CPU time 2.37 seconds
Started Apr 15 01:24:53 PM PDT 24
Finished Apr 15 01:24:56 PM PDT 24
Peak memory 222932 kb
Host smart-41e2bcc3-2305-490b-8057-c5d168984515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192855584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.192855584
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1676298608
Short name T160
Test name
Test status
Simulation time 4128606445 ps
CPU time 12.07 seconds
Started Apr 15 01:25:22 PM PDT 24
Finished Apr 15 01:25:34 PM PDT 24
Peak memory 219064 kb
Host smart-79c306eb-6995-4a8c-a95f-a881f0d86e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676298608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1676298608
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.648829291
Short name T290
Test name
Test status
Simulation time 54084851886 ps
CPU time 89.48 seconds
Started Apr 15 01:26:30 PM PDT 24
Finished Apr 15 01:28:00 PM PDT 24
Peak memory 235728 kb
Host smart-88db9191-06be-434c-a3fb-c0f078dcff89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648829291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.648829291
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1803750118
Short name T184
Test name
Test status
Simulation time 7261943499 ps
CPU time 16.72 seconds
Started Apr 15 01:22:46 PM PDT 24
Finished Apr 15 01:23:03 PM PDT 24
Peak memory 224236 kb
Host smart-62a6577a-f688-4504-baf3-614800cd6b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803750118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1803750118
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3657417474
Short name T260
Test name
Test status
Simulation time 29244448112 ps
CPU time 24.04 seconds
Started Apr 15 01:22:45 PM PDT 24
Finished Apr 15 01:23:10 PM PDT 24
Peak memory 218724 kb
Host smart-31f1bafb-3819-47c8-8100-3487cbcf4120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657417474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3657417474
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_upload.3223786692
Short name T239
Test name
Test status
Simulation time 14782798403 ps
CPU time 15.11 seconds
Started Apr 15 01:22:44 PM PDT 24
Finished Apr 15 01:23:00 PM PDT 24
Peak memory 235604 kb
Host smart-5b8ca73f-09f2-43fb-b7f0-4446c3b7c5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223786692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3223786692
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3495503906
Short name T68
Test name
Test status
Simulation time 333510979 ps
CPU time 6.67 seconds
Started Apr 15 01:26:47 PM PDT 24
Finished Apr 15 01:26:54 PM PDT 24
Peak memory 221832 kb
Host smart-ac1f0bad-bab5-4fad-a491-852871d6a778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495503906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3495503906
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2802350543
Short name T250
Test name
Test status
Simulation time 3753945444 ps
CPU time 3.91 seconds
Started Apr 15 01:26:50 PM PDT 24
Finished Apr 15 01:26:55 PM PDT 24
Peak memory 219368 kb
Host smart-fe028791-9aa8-4bb9-956b-23727c08a0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802350543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2802350543
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.875278810
Short name T186
Test name
Test status
Simulation time 710633129 ps
CPU time 2.48 seconds
Started Apr 15 01:27:22 PM PDT 24
Finished Apr 15 01:27:25 PM PDT 24
Peak memory 218628 kb
Host smart-14255e89-8c3e-4562-a95b-e210d995f9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875278810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.875278810
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.222773742
Short name T70
Test name
Test status
Simulation time 126843942 ps
CPU time 3.01 seconds
Started Apr 15 01:28:34 PM PDT 24
Finished Apr 15 01:28:37 PM PDT 24
Peak memory 218428 kb
Host smart-1d8c05d6-22f5-402e-ab18-dfcfc0ff7870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222773742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.222773742
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2797932324
Short name T206
Test name
Test status
Simulation time 237528664 ps
CPU time 2.52 seconds
Started Apr 15 01:28:58 PM PDT 24
Finished Apr 15 01:29:00 PM PDT 24
Peak memory 220324 kb
Host smart-e97f03c9-7b9e-4912-a08f-7268dcb557c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797932324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2797932324
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2380093686
Short name T78
Test name
Test status
Simulation time 85591907066 ps
CPU time 19.91 seconds
Started Apr 15 01:29:59 PM PDT 24
Finished Apr 15 01:30:19 PM PDT 24
Peak memory 222500 kb
Host smart-7253620c-f641-4126-9850-aefc1571d96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380093686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2380093686
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1728062109
Short name T234
Test name
Test status
Simulation time 3936683582 ps
CPU time 30.5 seconds
Started Apr 15 01:23:16 PM PDT 24
Finished Apr 15 01:23:47 PM PDT 24
Peak memory 235520 kb
Host smart-6668faa5-a039-4995-a449-91193d25778d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728062109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1728062109
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.4231346831
Short name T272
Test name
Test status
Simulation time 11091147642 ps
CPU time 8.53 seconds
Started Apr 15 01:23:14 PM PDT 24
Finished Apr 15 01:23:23 PM PDT 24
Peak memory 216964 kb
Host smart-c6054a5d-da3a-4d4b-abb3-e907347a072c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231346831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.4231346831
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_upload.1847136505
Short name T221
Test name
Test status
Simulation time 2777154149 ps
CPU time 4.05 seconds
Started Apr 15 01:23:22 PM PDT 24
Finished Apr 15 01:23:26 PM PDT 24
Peak memory 223100 kb
Host smart-340b7f8c-bc8c-4ad7-9d6c-4a989cbf9ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847136505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1847136505
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3339173936
Short name T269
Test name
Test status
Simulation time 120867642 ps
CPU time 4.5 seconds
Started Apr 15 01:23:31 PM PDT 24
Finished Apr 15 01:23:36 PM PDT 24
Peak memory 219044 kb
Host smart-5bc76ed9-1524-4c94-b9a7-0f4aaf11fb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339173936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3339173936
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3982670170
Short name T91
Test name
Test status
Simulation time 262826051 ps
CPU time 3.48 seconds
Started Apr 15 01:27:27 PM PDT 24
Finished Apr 15 01:27:31 PM PDT 24
Peak memory 223048 kb
Host smart-5c2cc87e-09a1-4241-8720-4b09d69ba1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982670170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3982670170
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3400714366
Short name T396
Test name
Test status
Simulation time 1803277191 ps
CPU time 14.55 seconds
Started Apr 15 01:23:54 PM PDT 24
Finished Apr 15 01:24:09 PM PDT 24
Peak memory 216588 kb
Host smart-2f5189dd-8789-4098-8c0f-e69c8a3d0fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400714366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3400714366
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3662790757
Short name T353
Test name
Test status
Simulation time 765417153 ps
CPU time 13.27 seconds
Started Apr 15 12:27:11 PM PDT 24
Finished Apr 15 12:27:25 PM PDT 24
Peak memory 215192 kb
Host smart-fd4343e4-2a4b-44f0-a65d-293d07b314ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662790757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3662790757
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2251219028
Short name T339
Test name
Test status
Simulation time 442229598 ps
CPU time 2.16 seconds
Started Apr 15 01:22:21 PM PDT 24
Finished Apr 15 01:22:23 PM PDT 24
Peak memory 216572 kb
Host smart-ea4ecb3c-91cd-43a5-bdee-50b1b766effc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251219028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2251219028
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_upload.927781951
Short name T172
Test name
Test status
Simulation time 5230753627 ps
CPU time 19.24 seconds
Started Apr 15 01:22:21 PM PDT 24
Finished Apr 15 01:22:41 PM PDT 24
Peak memory 224840 kb
Host smart-639f812f-20be-4a9b-99e0-7371709479c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927781951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.927781951
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3166869666
Short name T169
Test name
Test status
Simulation time 290795367 ps
CPU time 5.44 seconds
Started Apr 15 01:23:44 PM PDT 24
Finished Apr 15 01:23:49 PM PDT 24
Peak memory 222048 kb
Host smart-220b67eb-278c-45c8-8c91-58442701cd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166869666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3166869666
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3652630116
Short name T179
Test name
Test status
Simulation time 9131883624 ps
CPU time 23.45 seconds
Started Apr 15 01:23:48 PM PDT 24
Finished Apr 15 01:24:11 PM PDT 24
Peak memory 224108 kb
Host smart-42325b53-7091-4456-a12e-e03d0edc8036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652630116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3652630116
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2210983924
Short name T263
Test name
Test status
Simulation time 9738974569 ps
CPU time 24.77 seconds
Started Apr 15 01:23:44 PM PDT 24
Finished Apr 15 01:24:10 PM PDT 24
Peak memory 224816 kb
Host smart-ff0071bf-9fc2-4125-b1f7-fe0a24d3ae15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210983924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2210983924
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.248655090
Short name T237
Test name
Test status
Simulation time 262680923 ps
CPU time 3.78 seconds
Started Apr 15 01:23:53 PM PDT 24
Finished Apr 15 01:23:57 PM PDT 24
Peak memory 218660 kb
Host smart-25529331-702e-43fc-81c9-21806fae1605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248655090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.248655090
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1970144992
Short name T340
Test name
Test status
Simulation time 913207894 ps
CPU time 5.31 seconds
Started Apr 15 01:24:00 PM PDT 24
Finished Apr 15 01:24:05 PM PDT 24
Peak memory 223472 kb
Host smart-6cf1df12-a0e8-403f-bc04-d0bb62d1d19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970144992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1970144992
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.902269837
Short name T62
Test name
Test status
Simulation time 196274781 ps
CPU time 4.15 seconds
Started Apr 15 01:24:00 PM PDT 24
Finished Apr 15 01:24:04 PM PDT 24
Peak memory 218080 kb
Host smart-76e12abe-7257-4a6d-8413-4a948f58f98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902269837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.902269837
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1333335333
Short name T225
Test name
Test status
Simulation time 3562520750 ps
CPU time 9.99 seconds
Started Apr 15 01:24:16 PM PDT 24
Finished Apr 15 01:24:26 PM PDT 24
Peak memory 220848 kb
Host smart-fef39a2c-12b4-4ea7-bd5e-934f908d8487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333335333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1333335333
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2862663374
Short name T214
Test name
Test status
Simulation time 1393883126 ps
CPU time 6.61 seconds
Started Apr 15 01:24:41 PM PDT 24
Finished Apr 15 01:24:48 PM PDT 24
Peak memory 224308 kb
Host smart-4890e206-7be3-412f-8d2b-1774e1cf89bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862663374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2862663374
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.4153971284
Short name T330
Test name
Test status
Simulation time 2855864319 ps
CPU time 9.23 seconds
Started Apr 15 01:22:38 PM PDT 24
Finished Apr 15 01:22:49 PM PDT 24
Peak memory 233032 kb
Host smart-fe1aa8cc-6471-442d-a555-c025905524c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153971284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.4153971284
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3191768388
Short name T564
Test name
Test status
Simulation time 129147308 ps
CPU time 2.7 seconds
Started Apr 15 01:22:36 PM PDT 24
Finished Apr 15 01:22:39 PM PDT 24
Peak memory 218064 kb
Host smart-b8e8fa27-bbdb-4650-b02c-8e28462ddb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191768388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3191768388
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3411135339
Short name T342
Test name
Test status
Simulation time 186281456 ps
CPU time 3.27 seconds
Started Apr 15 01:25:09 PM PDT 24
Finished Apr 15 01:25:13 PM PDT 24
Peak memory 223324 kb
Host smart-08191b3a-69b6-49e3-abbf-a5463eb80c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411135339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3411135339
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_upload.2392596459
Short name T218
Test name
Test status
Simulation time 3409941687 ps
CPU time 15.23 seconds
Started Apr 15 01:25:12 PM PDT 24
Finished Apr 15 01:25:27 PM PDT 24
Peak memory 219516 kb
Host smart-f8007b0d-3423-4851-b963-57972e692c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392596459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2392596459
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2434279949
Short name T293
Test name
Test status
Simulation time 4882154560 ps
CPU time 75.57 seconds
Started Apr 15 01:25:24 PM PDT 24
Finished Apr 15 01:26:40 PM PDT 24
Peak memory 233020 kb
Host smart-2b2588f0-a2e2-4304-ac2e-eeae82e09426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434279949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2434279949
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.830893544
Short name T67
Test name
Test status
Simulation time 1836094634 ps
CPU time 2.31 seconds
Started Apr 15 01:25:19 PM PDT 24
Finished Apr 15 01:25:22 PM PDT 24
Peak memory 217056 kb
Host smart-ae76a80f-ba7b-4d88-b63a-066b5466ceb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830893544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.830893544
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3109317129
Short name T210
Test name
Test status
Simulation time 1127165154 ps
CPU time 3.36 seconds
Started Apr 15 01:25:36 PM PDT 24
Finished Apr 15 01:25:39 PM PDT 24
Peak memory 222900 kb
Host smart-15f9613f-c7a4-482a-a03f-7fc88baefcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109317129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3109317129
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3111255985
Short name T331
Test name
Test status
Simulation time 725577126 ps
CPU time 6.08 seconds
Started Apr 15 01:25:35 PM PDT 24
Finished Apr 15 01:25:42 PM PDT 24
Peak memory 239920 kb
Host smart-ec6881b4-e978-4682-abf6-ca4c473bd54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111255985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3111255985
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_intercept.864868336
Short name T92
Test name
Test status
Simulation time 74785820 ps
CPU time 2.56 seconds
Started Apr 15 01:26:06 PM PDT 24
Finished Apr 15 01:26:09 PM PDT 24
Peak memory 222956 kb
Host smart-e631df77-fb56-4b6a-9468-4e86cda3d711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864868336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.864868336
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.625844564
Short name T95
Test name
Test status
Simulation time 31021684939 ps
CPU time 38.84 seconds
Started Apr 15 01:26:10 PM PDT 24
Finished Apr 15 01:26:49 PM PDT 24
Peak memory 224748 kb
Host smart-21917d66-0412-4ac5-b413-d0dd2d2987e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625844564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.625844564
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3969083265
Short name T370
Test name
Test status
Simulation time 175440925 ps
CPU time 4.41 seconds
Started Apr 15 01:26:40 PM PDT 24
Finished Apr 15 01:26:45 PM PDT 24
Peak memory 219080 kb
Host smart-e1b7d01a-3c9c-4800-a11d-84021b83db9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969083265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3969083265
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2182273095
Short name T171
Test name
Test status
Simulation time 1744111645 ps
CPU time 4.48 seconds
Started Apr 15 01:26:41 PM PDT 24
Finished Apr 15 01:26:45 PM PDT 24
Peak memory 223120 kb
Host smart-a570f46c-a753-4843-8e0b-58e451c218cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182273095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2182273095
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_upload.1323109246
Short name T319
Test name
Test status
Simulation time 14013210981 ps
CPU time 40.37 seconds
Started Apr 15 01:26:52 PM PDT 24
Finished Apr 15 01:27:33 PM PDT 24
Peak memory 230268 kb
Host smart-8e09e052-1c63-4ee0-866d-5ef9fd44f750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323109246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1323109246
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3233747669
Short name T243
Test name
Test status
Simulation time 4190904995 ps
CPU time 20.72 seconds
Started Apr 15 01:27:17 PM PDT 24
Finished Apr 15 01:27:39 PM PDT 24
Peak memory 233044 kb
Host smart-fd08629b-2321-4a42-844f-bf887c8c395a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233747669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3233747669
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_intercept.821775255
Short name T307
Test name
Test status
Simulation time 394447329 ps
CPU time 4.56 seconds
Started Apr 15 01:27:18 PM PDT 24
Finished Apr 15 01:27:24 PM PDT 24
Peak memory 233452 kb
Host smart-61d9d270-bc92-4bb4-b8ed-694f8bfebf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821775255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.821775255
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.777988730
Short name T81
Test name
Test status
Simulation time 4025372924 ps
CPU time 32.35 seconds
Started Apr 15 01:27:26 PM PDT 24
Finished Apr 15 01:27:59 PM PDT 24
Peak memory 250304 kb
Host smart-a3dc8640-b3bf-460a-908e-3285d708b43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777988730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.777988730
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.253135890
Short name T338
Test name
Test status
Simulation time 5747323918 ps
CPU time 16.32 seconds
Started Apr 15 01:27:28 PM PDT 24
Finished Apr 15 01:27:44 PM PDT 24
Peak memory 222624 kb
Host smart-330efbae-1f5f-4d0a-af42-c861522d1be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253135890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.253135890
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.887167739
Short name T341
Test name
Test status
Simulation time 9684276406 ps
CPU time 25.3 seconds
Started Apr 15 01:27:51 PM PDT 24
Finished Apr 15 01:28:17 PM PDT 24
Peak memory 232924 kb
Host smart-1b406fa1-a6a2-4e67-ae3b-1f37939daa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887167739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.887167739
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1616442566
Short name T212
Test name
Test status
Simulation time 1017347043 ps
CPU time 6.73 seconds
Started Apr 15 01:22:53 PM PDT 24
Finished Apr 15 01:23:00 PM PDT 24
Peak memory 224704 kb
Host smart-46b5c8f5-03c5-4fca-ae43-07d4ea3d4ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616442566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1616442566
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.4138818333
Short name T344
Test name
Test status
Simulation time 2903793914 ps
CPU time 10.25 seconds
Started Apr 15 01:29:17 PM PDT 24
Finished Apr 15 01:29:28 PM PDT 24
Peak memory 227076 kb
Host smart-994ed9e2-70a5-4277-b830-741fbddbccc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138818333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.4138818333
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1490214701
Short name T337
Test name
Test status
Simulation time 4491665313 ps
CPU time 14.59 seconds
Started Apr 15 01:29:32 PM PDT 24
Finished Apr 15 01:29:47 PM PDT 24
Peak memory 223580 kb
Host smart-4130f55e-f72c-4e89-a0c9-a64e8599996f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490214701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1490214701
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2088803081
Short name T259
Test name
Test status
Simulation time 11753076603 ps
CPU time 11.34 seconds
Started Apr 15 01:29:45 PM PDT 24
Finished Apr 15 01:29:57 PM PDT 24
Peak memory 219092 kb
Host smart-17c92ff4-b1bf-44f3-ac83-fc37aca29d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088803081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2088803081
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.122781757
Short name T247
Test name
Test status
Simulation time 21743935071 ps
CPU time 171.98 seconds
Started Apr 15 01:30:00 PM PDT 24
Finished Apr 15 01:32:52 PM PDT 24
Peak memory 238248 kb
Host smart-ebed6521-3fe3-4750-808c-8a963d8bd57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122781757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.122781757
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2739340531
Short name T308
Test name
Test status
Simulation time 1563970235 ps
CPU time 5.92 seconds
Started Apr 15 01:29:59 PM PDT 24
Finished Apr 15 01:30:05 PM PDT 24
Peak memory 223084 kb
Host smart-06e0839a-0f97-4ad5-a37a-a485cbbbce04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739340531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2739340531
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2841444193
Short name T3
Test name
Test status
Simulation time 597744261 ps
CPU time 3.96 seconds
Started Apr 15 01:30:49 PM PDT 24
Finished Apr 15 01:30:53 PM PDT 24
Peak memory 218856 kb
Host smart-513f52c5-a6f5-492b-a8ef-5b3c02bdfc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841444193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2841444193
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1743247025
Short name T64
Test name
Test status
Simulation time 21471266290 ps
CPU time 31.02 seconds
Started Apr 15 01:31:07 PM PDT 24
Finished Apr 15 01:31:39 PM PDT 24
Peak memory 232968 kb
Host smart-d530cada-4f74-4d3f-bfae-83d48b60ffed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743247025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1743247025
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_upload.1472510119
Short name T205
Test name
Test status
Simulation time 203357245 ps
CPU time 2.53 seconds
Started Apr 15 01:23:00 PM PDT 24
Finished Apr 15 01:23:04 PM PDT 24
Peak memory 222164 kb
Host smart-21033b72-9a51-45e7-9142-107549c730bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472510119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1472510119
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.453937028
Short name T323
Test name
Test status
Simulation time 16985172243 ps
CPU time 44.38 seconds
Started Apr 15 01:23:06 PM PDT 24
Finished Apr 15 01:23:51 PM PDT 24
Peak memory 219024 kb
Host smart-73a37cc0-7e95-40af-8353-eb62c5c3ec4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453937028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.453937028
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2328797365
Short name T71
Test name
Test status
Simulation time 2598888205 ps
CPU time 15.46 seconds
Started Apr 15 01:23:05 PM PDT 24
Finished Apr 15 01:23:21 PM PDT 24
Peak memory 232688 kb
Host smart-b14d2234-52c8-4c2c-8df4-c1fd301aefdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328797365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2328797365
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_upload.3508695704
Short name T187
Test name
Test status
Simulation time 4382455916 ps
CPU time 15.13 seconds
Started Apr 15 01:23:16 PM PDT 24
Finished Apr 15 01:23:31 PM PDT 24
Peak memory 223516 kb
Host smart-f283bb55-a799-4563-9ea6-39148ea9f727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508695704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3508695704
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3280534479
Short name T101
Test name
Test status
Simulation time 42787999 ps
CPU time 1.33 seconds
Started Apr 15 12:26:44 PM PDT 24
Finished Apr 15 12:26:46 PM PDT 24
Peak memory 216304 kb
Host smart-a7f2b8f8-908b-429a-a07a-dbbd6410af81
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280534479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3280534479
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.525155098
Short name T426
Test name
Test status
Simulation time 4565164303 ps
CPU time 19.23 seconds
Started Apr 15 01:23:39 PM PDT 24
Finished Apr 15 01:23:59 PM PDT 24
Peak memory 219048 kb
Host smart-c3be3dc7-d1ad-422d-87a3-0bcb735c527b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=525155098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.525155098
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1342005654
Short name T155
Test name
Test status
Simulation time 437756199 ps
CPU time 9 seconds
Started Apr 15 12:26:48 PM PDT 24
Finished Apr 15 12:26:57 PM PDT 24
Peak memory 215176 kb
Host smart-8a2d6648-cfae-49eb-abe1-be0a0ecbc1d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342005654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1342005654
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3334907167
Short name T820
Test name
Test status
Simulation time 375877180 ps
CPU time 22.17 seconds
Started Apr 15 12:26:43 PM PDT 24
Finished Apr 15 12:27:06 PM PDT 24
Peak memory 207036 kb
Host smart-dd757ed7-1f92-41f2-85af-c8a3b5903b19
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334907167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3334907167
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1244817946
Short name T808
Test name
Test status
Simulation time 520300838 ps
CPU time 3.73 seconds
Started Apr 15 12:26:43 PM PDT 24
Finished Apr 15 12:26:47 PM PDT 24
Peak memory 217056 kb
Host smart-53de4f3c-6343-4230-a902-93ec14cf5f6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244817946 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1244817946
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1882136596
Short name T857
Test name
Test status
Simulation time 17086949 ps
CPU time 0.73 seconds
Started Apr 15 12:26:45 PM PDT 24
Finished Apr 15 12:26:46 PM PDT 24
Peak memory 203616 kb
Host smart-b8c7c65e-8293-43d8-b97b-c305d5f2966e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882136596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
882136596
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.333532267
Short name T138
Test name
Test status
Simulation time 47554637 ps
CPU time 1.64 seconds
Started Apr 15 12:26:44 PM PDT 24
Finished Apr 15 12:26:47 PM PDT 24
Peak memory 215316 kb
Host smart-c8c5b0aa-59a1-4c1a-9ed1-f33c433e7ab5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333532267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.333532267
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2108803226
Short name T847
Test name
Test status
Simulation time 12329714 ps
CPU time 0.66 seconds
Started Apr 15 12:26:42 PM PDT 24
Finished Apr 15 12:26:43 PM PDT 24
Peak memory 203328 kb
Host smart-88c48b47-a05b-4e9f-8450-151ba86060c0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108803226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2108803226
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4248040042
Short name T771
Test name
Test status
Simulation time 59672134 ps
CPU time 3.68 seconds
Started Apr 15 12:26:44 PM PDT 24
Finished Apr 15 12:26:48 PM PDT 24
Peak memory 215256 kb
Host smart-8d2c0655-8fa3-45ab-a67f-889486173467
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248040042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.4248040042
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2427755852
Short name T124
Test name
Test status
Simulation time 194939312 ps
CPU time 4.11 seconds
Started Apr 15 12:26:51 PM PDT 24
Finished Apr 15 12:26:56 PM PDT 24
Peak memory 215312 kb
Host smart-f9f95c48-0ac5-4167-afd9-6e8f289f23a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427755852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
427755852
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1984950162
Short name T785
Test name
Test status
Simulation time 2761283829 ps
CPU time 15.38 seconds
Started Apr 15 12:26:42 PM PDT 24
Finished Apr 15 12:26:57 PM PDT 24
Peak memory 216540 kb
Host smart-862a18b8-90dc-4ffb-908b-96f10c9a3b5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984950162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1984950162
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4270828292
Short name T149
Test name
Test status
Simulation time 12017446656 ps
CPU time 14.87 seconds
Started Apr 15 12:26:50 PM PDT 24
Finished Apr 15 12:27:05 PM PDT 24
Peak memory 215396 kb
Host smart-59249c6f-0694-4cc7-95f4-15a3c676cfcf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270828292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.4270828292
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3316105136
Short name T148
Test name
Test status
Simulation time 10829498669 ps
CPU time 37.96 seconds
Started Apr 15 12:26:43 PM PDT 24
Finished Apr 15 12:27:22 PM PDT 24
Peak memory 207096 kb
Host smart-4aede501-2564-49e9-a89c-4bcfe3f6b8e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316105136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3316105136
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2457502980
Short name T126
Test name
Test status
Simulation time 71616325 ps
CPU time 1 seconds
Started Apr 15 12:26:44 PM PDT 24
Finished Apr 15 12:26:45 PM PDT 24
Peak memory 206712 kb
Host smart-1bc974cf-8a6d-4a4d-9626-33a6996a2770
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457502980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2457502980
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2912561111
Short name T809
Test name
Test status
Simulation time 119207951 ps
CPU time 2.76 seconds
Started Apr 15 12:26:41 PM PDT 24
Finished Apr 15 12:26:44 PM PDT 24
Peak memory 216428 kb
Host smart-db68014b-2fa6-40bd-a5e2-73f67e6790b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912561111 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2912561111
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2943895054
Short name T151
Test name
Test status
Simulation time 50875408 ps
CPU time 1.28 seconds
Started Apr 15 12:26:44 PM PDT 24
Finished Apr 15 12:26:46 PM PDT 24
Peak memory 207048 kb
Host smart-cea6e377-b935-466c-8a5a-86d46bcef579
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943895054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
943895054
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3529017829
Short name T769
Test name
Test status
Simulation time 16640975 ps
CPU time 0.75 seconds
Started Apr 15 12:26:44 PM PDT 24
Finished Apr 15 12:26:45 PM PDT 24
Peak memory 203352 kb
Host smart-ad0a13e6-da51-41dd-ba87-5c820ea201b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529017829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
529017829
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4046155333
Short name T825
Test name
Test status
Simulation time 17352552 ps
CPU time 1.27 seconds
Started Apr 15 12:26:46 PM PDT 24
Finished Apr 15 12:26:47 PM PDT 24
Peak memory 215296 kb
Host smart-61351320-3226-430a-a2d2-c0db7a8c74e0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046155333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4046155333
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1290282346
Short name T841
Test name
Test status
Simulation time 12136139 ps
CPU time 0.64 seconds
Started Apr 15 12:26:50 PM PDT 24
Finished Apr 15 12:26:51 PM PDT 24
Peak memory 203644 kb
Host smart-e940692f-c1c1-4e15-95f3-666ace1fe51f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290282346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1290282346
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2597690151
Short name T854
Test name
Test status
Simulation time 205415325 ps
CPU time 2.8 seconds
Started Apr 15 12:26:44 PM PDT 24
Finished Apr 15 12:26:48 PM PDT 24
Peak memory 215296 kb
Host smart-78794349-623a-4681-8a91-aa55171844be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597690151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2597690151
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4283765015
Short name T821
Test name
Test status
Simulation time 257594845 ps
CPU time 3.09 seconds
Started Apr 15 12:26:49 PM PDT 24
Finished Apr 15 12:26:53 PM PDT 24
Peak memory 216324 kb
Host smart-0165fa62-4269-4c72-a3b7-a310789a96db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283765015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
283765015
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.741296469
Short name T843
Test name
Test status
Simulation time 1431099142 ps
CPU time 7.1 seconds
Started Apr 15 12:26:44 PM PDT 24
Finished Apr 15 12:26:52 PM PDT 24
Peak memory 215244 kb
Host smart-33c097e1-6ee6-4517-a049-3af7a824454a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741296469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.741296469
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2971747035
Short name T838
Test name
Test status
Simulation time 182017222 ps
CPU time 2.56 seconds
Started Apr 15 12:27:12 PM PDT 24
Finished Apr 15 12:27:16 PM PDT 24
Peak memory 216780 kb
Host smart-bbd3a427-e230-4fef-a0fe-0b48897ee739
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971747035 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2971747035
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1615579322
Short name T152
Test name
Test status
Simulation time 120283125 ps
CPU time 1.21 seconds
Started Apr 15 12:27:08 PM PDT 24
Finished Apr 15 12:27:10 PM PDT 24
Peak memory 207176 kb
Host smart-b273de2a-bcf2-43dd-a5bf-bff65b2eb77a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615579322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1615579322
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3582008195
Short name T823
Test name
Test status
Simulation time 25887142 ps
CPU time 0.7 seconds
Started Apr 15 12:27:11 PM PDT 24
Finished Apr 15 12:27:12 PM PDT 24
Peak memory 203360 kb
Host smart-361a9ee8-9357-4f10-9619-57676d0f8a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582008195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3582008195
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1888931911
Short name T34
Test name
Test status
Simulation time 297973188 ps
CPU time 1.94 seconds
Started Apr 15 12:27:08 PM PDT 24
Finished Apr 15 12:27:10 PM PDT 24
Peak memory 215224 kb
Host smart-d29a5916-6e5d-4896-ac90-41b95a3f1256
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888931911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1888931911
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.929749796
Short name T128
Test name
Test status
Simulation time 155772747 ps
CPU time 4.53 seconds
Started Apr 15 12:27:16 PM PDT 24
Finished Apr 15 12:27:21 PM PDT 24
Peak memory 215468 kb
Host smart-68b236f3-0a25-4401-a27a-811c9eb8dbe7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929749796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.929749796
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2280383570
Short name T767
Test name
Test status
Simulation time 54081936 ps
CPU time 1.97 seconds
Started Apr 15 12:27:14 PM PDT 24
Finished Apr 15 12:27:17 PM PDT 24
Peak memory 216272 kb
Host smart-56b5916c-659d-495b-a422-79de9ebfae9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280383570 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2280383570
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1042171601
Short name T764
Test name
Test status
Simulation time 36676437 ps
CPU time 1.33 seconds
Started Apr 15 12:27:19 PM PDT 24
Finished Apr 15 12:27:21 PM PDT 24
Peak memory 207108 kb
Host smart-d5f913fe-3b1b-46f1-8ad2-83e15cd8c0d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042171601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1042171601
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2261165370
Short name T746
Test name
Test status
Simulation time 13347489 ps
CPU time 0.7 seconds
Started Apr 15 12:27:12 PM PDT 24
Finished Apr 15 12:27:13 PM PDT 24
Peak memory 203316 kb
Host smart-4fcbaa44-4a11-401b-8d9f-fedd9b5d7f44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261165370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2261165370
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3339097282
Short name T845
Test name
Test status
Simulation time 2892153871 ps
CPU time 3.99 seconds
Started Apr 15 12:27:14 PM PDT 24
Finished Apr 15 12:27:18 PM PDT 24
Peak memory 215384 kb
Host smart-ad773c6b-0cb0-4174-94e9-030eb3ad8f21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339097282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3339097282
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1102185761
Short name T354
Test name
Test status
Simulation time 3212702245 ps
CPU time 19.38 seconds
Started Apr 15 12:27:14 PM PDT 24
Finished Apr 15 12:27:34 PM PDT 24
Peak memory 216560 kb
Host smart-333f633a-ce34-4aaa-a2c6-8ea41aba154b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102185761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1102185761
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1187112934
Short name T796
Test name
Test status
Simulation time 78997944 ps
CPU time 2.44 seconds
Started Apr 15 12:27:14 PM PDT 24
Finished Apr 15 12:27:17 PM PDT 24
Peak memory 216364 kb
Host smart-ffea88b4-21da-4a47-9e69-50166803abf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187112934 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1187112934
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3689955657
Short name T142
Test name
Test status
Simulation time 224186262 ps
CPU time 2.64 seconds
Started Apr 15 12:27:15 PM PDT 24
Finished Apr 15 12:27:18 PM PDT 24
Peak memory 207024 kb
Host smart-cd2ef7f6-9f31-40a2-935a-175994f49822
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689955657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3689955657
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1020477266
Short name T753
Test name
Test status
Simulation time 51910532 ps
CPU time 0.68 seconds
Started Apr 15 12:27:19 PM PDT 24
Finished Apr 15 12:27:20 PM PDT 24
Peak memory 203272 kb
Host smart-f2a72692-96d0-4b61-ac45-b6b76f9754e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020477266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1020477266
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.907751484
Short name T153
Test name
Test status
Simulation time 45147841 ps
CPU time 2.66 seconds
Started Apr 15 12:27:19 PM PDT 24
Finished Apr 15 12:27:22 PM PDT 24
Peak memory 215280 kb
Host smart-eea7e667-a6af-4707-92e8-f4311d27e1b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907751484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.907751484
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4180654351
Short name T111
Test name
Test status
Simulation time 739305970 ps
CPU time 3.01 seconds
Started Apr 15 12:27:15 PM PDT 24
Finished Apr 15 12:27:18 PM PDT 24
Peak memory 215336 kb
Host smart-5a56a2fe-2829-479d-8811-5d9b73a574cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180654351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
4180654351
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3805881040
Short name T851
Test name
Test status
Simulation time 1069857357 ps
CPU time 6.39 seconds
Started Apr 15 12:27:28 PM PDT 24
Finished Apr 15 12:27:35 PM PDT 24
Peak memory 215260 kb
Host smart-73859767-eb9e-4702-87dc-081211305107
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805881040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3805881040
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4122291919
Short name T762
Test name
Test status
Simulation time 96250084 ps
CPU time 1.63 seconds
Started Apr 15 12:27:19 PM PDT 24
Finished Apr 15 12:27:21 PM PDT 24
Peak memory 215196 kb
Host smart-63467548-b967-44b0-be52-f8e5448de6a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122291919 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.4122291919
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1387403052
Short name T140
Test name
Test status
Simulation time 87338888 ps
CPU time 1.99 seconds
Started Apr 15 12:27:14 PM PDT 24
Finished Apr 15 12:27:17 PM PDT 24
Peak memory 207036 kb
Host smart-6d38670d-e6de-416d-b121-2ecbf23f9104
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387403052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1387403052
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1213397881
Short name T159
Test name
Test status
Simulation time 73106555 ps
CPU time 0.71 seconds
Started Apr 15 12:27:16 PM PDT 24
Finished Apr 15 12:27:17 PM PDT 24
Peak memory 203324 kb
Host smart-3ed79537-7a08-4b62-80c6-809b85b1dbe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213397881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1213397881
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2478945602
Short name T824
Test name
Test status
Simulation time 102884531 ps
CPU time 1.71 seconds
Started Apr 15 12:27:16 PM PDT 24
Finished Apr 15 12:27:18 PM PDT 24
Peak memory 207048 kb
Host smart-70521ce3-329d-401c-a65a-a6a9a869263d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478945602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2478945602
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1695378964
Short name T833
Test name
Test status
Simulation time 84213648 ps
CPU time 1.66 seconds
Started Apr 15 12:27:20 PM PDT 24
Finished Apr 15 12:27:23 PM PDT 24
Peak memory 212932 kb
Host smart-c9b77792-dc12-48d2-a528-a5f7c0d0f888
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695378964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1695378964
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1457506509
Short name T791
Test name
Test status
Simulation time 160750112 ps
CPU time 2.97 seconds
Started Apr 15 12:27:15 PM PDT 24
Finished Apr 15 12:27:19 PM PDT 24
Peak memory 216768 kb
Host smart-6d5d1200-aab1-4678-8f46-232c1c2f4e30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457506509 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1457506509
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.523586508
Short name T139
Test name
Test status
Simulation time 39326319 ps
CPU time 2.49 seconds
Started Apr 15 12:27:18 PM PDT 24
Finished Apr 15 12:27:21 PM PDT 24
Peak memory 207100 kb
Host smart-e2d93a4c-7dd8-46ff-a60b-2146ee243b74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523586508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.523586508
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3833762277
Short name T794
Test name
Test status
Simulation time 19116840 ps
CPU time 0.68 seconds
Started Apr 15 12:27:17 PM PDT 24
Finished Apr 15 12:27:19 PM PDT 24
Peak memory 203296 kb
Host smart-c52fe842-bbdf-429e-a1f9-504b31b3d3fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833762277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3833762277
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3388089500
Short name T33
Test name
Test status
Simulation time 119437776 ps
CPU time 1.65 seconds
Started Apr 15 12:27:20 PM PDT 24
Finished Apr 15 12:27:23 PM PDT 24
Peak memory 212732 kb
Host smart-a3083af8-0447-4090-83bf-98a86f18db5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388089500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3388089500
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2586367289
Short name T119
Test name
Test status
Simulation time 191761508 ps
CPU time 3.84 seconds
Started Apr 15 12:27:20 PM PDT 24
Finished Apr 15 12:27:25 PM PDT 24
Peak memory 212840 kb
Host smart-80372b9c-2717-462d-a42e-efe9be45a417
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586367289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2586367289
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3405738584
Short name T859
Test name
Test status
Simulation time 219080350 ps
CPU time 13.03 seconds
Started Apr 15 12:27:14 PM PDT 24
Finished Apr 15 12:27:27 PM PDT 24
Peak memory 215360 kb
Host smart-f4d920db-8ec8-46d0-b97c-0eeaa2fd1beb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405738584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3405738584
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3950139753
Short name T125
Test name
Test status
Simulation time 133451502 ps
CPU time 2.48 seconds
Started Apr 15 12:27:16 PM PDT 24
Finished Apr 15 12:27:18 PM PDT 24
Peak memory 216792 kb
Host smart-9a690075-ca96-4aa7-a139-a6965bad92d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950139753 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3950139753
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1439819133
Short name T141
Test name
Test status
Simulation time 115584181 ps
CPU time 1.82 seconds
Started Apr 15 12:27:14 PM PDT 24
Finished Apr 15 12:27:16 PM PDT 24
Peak memory 207104 kb
Host smart-4d4af3c8-26fc-47d2-9f8e-8ae82d1fd7ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439819133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1439819133
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.565014462
Short name T836
Test name
Test status
Simulation time 14551832 ps
CPU time 0.69 seconds
Started Apr 15 12:27:19 PM PDT 24
Finished Apr 15 12:27:20 PM PDT 24
Peak memory 203296 kb
Host smart-fc6d476d-7988-49c9-be18-f72ab8c8a6b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565014462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.565014462
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3444309789
Short name T819
Test name
Test status
Simulation time 27695347 ps
CPU time 1.75 seconds
Started Apr 15 12:27:20 PM PDT 24
Finished Apr 15 12:27:23 PM PDT 24
Peak memory 213220 kb
Host smart-5ddc020d-03f2-4f44-a1d2-3b40786a8791
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444309789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3444309789
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1995662504
Short name T787
Test name
Test status
Simulation time 228147615 ps
CPU time 3.37 seconds
Started Apr 15 12:27:16 PM PDT 24
Finished Apr 15 12:27:20 PM PDT 24
Peak memory 218620 kb
Host smart-85c4e1f3-b284-4a10-af00-3dbc61b67b81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995662504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1995662504
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2897369196
Short name T835
Test name
Test status
Simulation time 786929645 ps
CPU time 7.52 seconds
Started Apr 15 12:27:19 PM PDT 24
Finished Apr 15 12:27:27 PM PDT 24
Peak memory 215396 kb
Host smart-b56aa3b2-950e-4df0-8e65-7302d9ae03b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897369196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2897369196
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4240381927
Short name T774
Test name
Test status
Simulation time 141763943 ps
CPU time 3.47 seconds
Started Apr 15 12:27:22 PM PDT 24
Finished Apr 15 12:27:26 PM PDT 24
Peak memory 216308 kb
Host smart-21ef2b62-77c9-4527-bb43-857a67577927
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240381927 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.4240381927
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.520376037
Short name T839
Test name
Test status
Simulation time 564576034 ps
CPU time 2.68 seconds
Started Apr 15 12:27:23 PM PDT 24
Finished Apr 15 12:27:26 PM PDT 24
Peak memory 206792 kb
Host smart-316043f7-8114-40e7-b101-c35e8c873ad9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520376037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.520376037
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1891449226
Short name T850
Test name
Test status
Simulation time 10943501 ps
CPU time 0.69 seconds
Started Apr 15 12:27:14 PM PDT 24
Finished Apr 15 12:27:15 PM PDT 24
Peak memory 203648 kb
Host smart-1f862de8-1e59-4262-a237-317fa895f188
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891449226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1891449226
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2645414004
Short name T818
Test name
Test status
Simulation time 169517388 ps
CPU time 3.58 seconds
Started Apr 15 12:27:18 PM PDT 24
Finished Apr 15 12:27:22 PM PDT 24
Peak memory 215156 kb
Host smart-9173ba46-67fb-4bdb-8f78-e03deedade7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645414004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2645414004
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1655089980
Short name T134
Test name
Test status
Simulation time 2100782294 ps
CPU time 22.86 seconds
Started Apr 15 12:27:19 PM PDT 24
Finished Apr 15 12:27:42 PM PDT 24
Peak memory 215284 kb
Host smart-b317b450-431e-4030-9fb6-c776a3cd832e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655089980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1655089980
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1108574560
Short name T129
Test name
Test status
Simulation time 153723339 ps
CPU time 3.7 seconds
Started Apr 15 12:27:20 PM PDT 24
Finished Apr 15 12:27:24 PM PDT 24
Peak memory 217036 kb
Host smart-b42ad930-fcd5-4b8f-b381-1836f49ad000
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108574560 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1108574560
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1930682282
Short name T790
Test name
Test status
Simulation time 65486445 ps
CPU time 1.98 seconds
Started Apr 15 12:27:21 PM PDT 24
Finished Apr 15 12:27:24 PM PDT 24
Peak memory 215228 kb
Host smart-0e206109-f8c3-4a86-881a-ecd6a232a14c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930682282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1930682282
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3836041755
Short name T797
Test name
Test status
Simulation time 16468860 ps
CPU time 0.76 seconds
Started Apr 15 12:27:20 PM PDT 24
Finished Apr 15 12:27:21 PM PDT 24
Peak memory 203404 kb
Host smart-12c6d53c-b5f6-4909-a041-c39ae1a5ee56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836041755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3836041755
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2223293766
Short name T773
Test name
Test status
Simulation time 41326973 ps
CPU time 2.71 seconds
Started Apr 15 12:27:19 PM PDT 24
Finished Apr 15 12:27:23 PM PDT 24
Peak memory 215156 kb
Host smart-b86f5dd2-e857-47e8-9a01-5a185f3ec5af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223293766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2223293766
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.376540098
Short name T816
Test name
Test status
Simulation time 823373704 ps
CPU time 2.2 seconds
Started Apr 15 12:27:18 PM PDT 24
Finished Apr 15 12:27:21 PM PDT 24
Peak memory 215420 kb
Host smart-906b5acb-b160-4c25-8fb5-224c370db24c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376540098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.376540098
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4189229880
Short name T834
Test name
Test status
Simulation time 494362252 ps
CPU time 2.56 seconds
Started Apr 15 12:27:23 PM PDT 24
Finished Apr 15 12:27:26 PM PDT 24
Peak memory 216164 kb
Host smart-17d46e83-ba5b-4e26-b20f-35ad0618719e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189229880 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4189229880
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1246763923
Short name T135
Test name
Test status
Simulation time 36567829 ps
CPU time 2.26 seconds
Started Apr 15 12:27:22 PM PDT 24
Finished Apr 15 12:27:25 PM PDT 24
Peak memory 215308 kb
Host smart-5aae292b-3a95-47ed-b5c9-603f6cf58eab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246763923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1246763923
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.990147101
Short name T786
Test name
Test status
Simulation time 60980652 ps
CPU time 0.75 seconds
Started Apr 15 12:27:25 PM PDT 24
Finished Apr 15 12:27:26 PM PDT 24
Peak memory 203264 kb
Host smart-b480ace3-aa51-4ee3-b423-d65dc1a9d876
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990147101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.990147101
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.992905628
Short name T756
Test name
Test status
Simulation time 63164686 ps
CPU time 1.8 seconds
Started Apr 15 12:27:18 PM PDT 24
Finished Apr 15 12:27:20 PM PDT 24
Peak memory 216380 kb
Host smart-5cca760c-ffe6-466e-beab-dc77bd471b92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992905628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.992905628
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.355970716
Short name T817
Test name
Test status
Simulation time 68554273 ps
CPU time 2.25 seconds
Started Apr 15 12:27:21 PM PDT 24
Finished Apr 15 12:27:24 PM PDT 24
Peak memory 215456 kb
Host smart-c7d8866d-8e96-4d92-9643-d4458570bb63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355970716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.355970716
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2024318538
Short name T848
Test name
Test status
Simulation time 832935185 ps
CPU time 23.81 seconds
Started Apr 15 12:27:18 PM PDT 24
Finished Apr 15 12:27:43 PM PDT 24
Peak memory 215268 kb
Host smart-c24e1aee-9847-41f9-8df8-1eedfa8ae2fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024318538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2024318538
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1536712116
Short name T779
Test name
Test status
Simulation time 162823584 ps
CPU time 2.4 seconds
Started Apr 15 12:27:21 PM PDT 24
Finished Apr 15 12:27:24 PM PDT 24
Peak memory 216380 kb
Host smart-5db87d9b-149c-4c74-b05b-0a8de3997ad9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536712116 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1536712116
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2681359147
Short name T849
Test name
Test status
Simulation time 124460984 ps
CPU time 2.51 seconds
Started Apr 15 12:27:25 PM PDT 24
Finished Apr 15 12:27:28 PM PDT 24
Peak memory 215280 kb
Host smart-4b73fcc8-41d0-4b8b-82d8-40eb9f917a72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681359147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2681359147
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3553314905
Short name T826
Test name
Test status
Simulation time 52437788 ps
CPU time 0.73 seconds
Started Apr 15 12:27:17 PM PDT 24
Finished Apr 15 12:27:18 PM PDT 24
Peak memory 203280 kb
Host smart-410ed07a-eedb-4785-ac0e-eaf4a2eeac8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553314905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3553314905
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.12636173
Short name T755
Test name
Test status
Simulation time 52542356 ps
CPU time 1.82 seconds
Started Apr 15 12:27:18 PM PDT 24
Finished Apr 15 12:27:20 PM PDT 24
Peak memory 206900 kb
Host smart-b23bca61-983d-4852-90ee-746b68910766
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12636173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sp
i_device_same_csr_outstanding.12636173
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2332908159
Short name T127
Test name
Test status
Simulation time 130232894 ps
CPU time 3.09 seconds
Started Apr 15 12:27:24 PM PDT 24
Finished Apr 15 12:27:28 PM PDT 24
Peak memory 215344 kb
Host smart-604775d7-26c2-4a49-934e-4b747c17c609
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332908159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2332908159
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2040449379
Short name T350
Test name
Test status
Simulation time 1679308268 ps
CPU time 19.38 seconds
Started Apr 15 12:27:19 PM PDT 24
Finished Apr 15 12:27:39 PM PDT 24
Peak memory 215304 kb
Host smart-9aa800c9-ba4a-4b2f-b508-6fa73619dccf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040449379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2040449379
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.774448893
Short name T744
Test name
Test status
Simulation time 224808739 ps
CPU time 15.02 seconds
Started Apr 15 12:26:44 PM PDT 24
Finished Apr 15 12:27:00 PM PDT 24
Peak memory 215284 kb
Host smart-d43891fe-2e61-455e-89f4-1ac1b62c85b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774448893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.774448893
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.385843849
Short name T143
Test name
Test status
Simulation time 524619604 ps
CPU time 33.23 seconds
Started Apr 15 12:26:51 PM PDT 24
Finished Apr 15 12:27:25 PM PDT 24
Peak memory 207072 kb
Host smart-90672d74-db35-4273-9bbf-28602bb56c2c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385843849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.385843849
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3672986338
Short name T861
Test name
Test status
Simulation time 41558695 ps
CPU time 1.47 seconds
Started Apr 15 12:26:43 PM PDT 24
Finished Apr 15 12:26:45 PM PDT 24
Peak memory 216580 kb
Host smart-54149770-32e1-4adf-8cb7-565182c7e2f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672986338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3672986338
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3952845331
Short name T855
Test name
Test status
Simulation time 25719300 ps
CPU time 1.67 seconds
Started Apr 15 12:26:57 PM PDT 24
Finished Apr 15 12:26:59 PM PDT 24
Peak memory 215332 kb
Host smart-dcf52c46-8662-45ce-9fc3-e887ecc1631d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952845331 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3952845331
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4186424208
Short name T860
Test name
Test status
Simulation time 103767056 ps
CPU time 2.45 seconds
Started Apr 15 12:26:50 PM PDT 24
Finished Apr 15 12:26:53 PM PDT 24
Peak memory 215260 kb
Host smart-96eae83c-205c-4c96-99be-a7798e5c3b16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186424208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
186424208
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1885981637
Short name T768
Test name
Test status
Simulation time 43222675 ps
CPU time 0.7 seconds
Started Apr 15 12:26:50 PM PDT 24
Finished Apr 15 12:26:51 PM PDT 24
Peak memory 203248 kb
Host smart-25761dec-1fe7-489a-b826-3d80e23dacf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885981637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
885981637
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3354744659
Short name T146
Test name
Test status
Simulation time 133618798 ps
CPU time 1.24 seconds
Started Apr 15 12:26:47 PM PDT 24
Finished Apr 15 12:26:49 PM PDT 24
Peak memory 215256 kb
Host smart-45a6d3a8-6c5b-4ff0-a75a-ad9596560e58
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354744659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3354744659
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.814126163
Short name T804
Test name
Test status
Simulation time 12365264 ps
CPU time 0.64 seconds
Started Apr 15 12:26:50 PM PDT 24
Finished Apr 15 12:26:52 PM PDT 24
Peak memory 203284 kb
Host smart-1317c92c-0ad2-4718-8727-6c410b34388f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814126163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.814126163
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3749546827
Short name T150
Test name
Test status
Simulation time 394929586 ps
CPU time 4.09 seconds
Started Apr 15 12:26:48 PM PDT 24
Finished Apr 15 12:26:53 PM PDT 24
Peak memory 215268 kb
Host smart-40a77ec8-1b6d-451e-af63-aec229d522e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749546827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3749546827
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3776766291
Short name T810
Test name
Test status
Simulation time 107598195 ps
CPU time 3.11 seconds
Started Apr 15 12:26:43 PM PDT 24
Finished Apr 15 12:26:47 PM PDT 24
Peak memory 215348 kb
Host smart-b2d5fde5-dc90-4c01-af42-77a8d9729c87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776766291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
776766291
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4226428714
Short name T349
Test name
Test status
Simulation time 604602169 ps
CPU time 17.83 seconds
Started Apr 15 12:26:50 PM PDT 24
Finished Apr 15 12:27:09 PM PDT 24
Peak memory 215268 kb
Host smart-9dbc6ef3-2fa4-4474-8ac5-ab7de9ba8a76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226428714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.4226428714
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3441847637
Short name T830
Test name
Test status
Simulation time 30679988 ps
CPU time 0.7 seconds
Started Apr 15 12:27:20 PM PDT 24
Finished Apr 15 12:27:22 PM PDT 24
Peak memory 203608 kb
Host smart-97453cb1-704d-4542-8246-0f1162a893d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441847637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3441847637
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.750105699
Short name T780
Test name
Test status
Simulation time 14579240 ps
CPU time 0.72 seconds
Started Apr 15 12:27:21 PM PDT 24
Finished Apr 15 12:27:23 PM PDT 24
Peak memory 203316 kb
Host smart-58daf4cb-efdc-4a5e-9be6-47e082ff9eaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750105699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.750105699
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2424492926
Short name T751
Test name
Test status
Simulation time 33671745 ps
CPU time 0.72 seconds
Started Apr 15 12:27:21 PM PDT 24
Finished Apr 15 12:27:22 PM PDT 24
Peak memory 203304 kb
Host smart-f133d404-bfa0-48aa-9e4d-b8b9b6b25fa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424492926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2424492926
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1661090561
Short name T813
Test name
Test status
Simulation time 49578506 ps
CPU time 0.68 seconds
Started Apr 15 12:27:18 PM PDT 24
Finished Apr 15 12:27:20 PM PDT 24
Peak memory 203612 kb
Host smart-d0952b27-e5dd-4c2b-8faa-f6b19bdab1ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661090561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1661090561
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1692365805
Short name T760
Test name
Test status
Simulation time 13508913 ps
CPU time 0.7 seconds
Started Apr 15 12:27:19 PM PDT 24
Finished Apr 15 12:27:20 PM PDT 24
Peak memory 203608 kb
Host smart-7868c294-f51e-4175-90a3-fad1807dea0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692365805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1692365805
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2762552176
Short name T757
Test name
Test status
Simulation time 84777300 ps
CPU time 0.74 seconds
Started Apr 15 12:27:21 PM PDT 24
Finished Apr 15 12:27:23 PM PDT 24
Peak memory 203468 kb
Host smart-c8f77985-7b60-41c6-8744-7b701f6fcb89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762552176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2762552176
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.813109772
Short name T754
Test name
Test status
Simulation time 13171110 ps
CPU time 0.75 seconds
Started Apr 15 12:27:21 PM PDT 24
Finished Apr 15 12:27:22 PM PDT 24
Peak memory 203552 kb
Host smart-ea76dc2d-8c9b-40f3-b816-7381e9cc8b79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813109772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.813109772
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.109502289
Short name T750
Test name
Test status
Simulation time 75257436 ps
CPU time 0.81 seconds
Started Apr 15 12:27:20 PM PDT 24
Finished Apr 15 12:27:21 PM PDT 24
Peak memory 203556 kb
Host smart-3f56a353-5d20-432e-af45-446c449fa33a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109502289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.109502289
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1521398823
Short name T811
Test name
Test status
Simulation time 50175571 ps
CPU time 0.74 seconds
Started Apr 15 12:27:20 PM PDT 24
Finished Apr 15 12:27:22 PM PDT 24
Peak memory 203628 kb
Host smart-9b0ab10e-6e5d-4307-9093-b80ccc3585a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521398823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1521398823
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1821526928
Short name T743
Test name
Test status
Simulation time 44604240 ps
CPU time 0.67 seconds
Started Apr 15 12:27:26 PM PDT 24
Finished Apr 15 12:27:28 PM PDT 24
Peak memory 203608 kb
Host smart-3ea23872-8d1d-4a11-ac5a-30bc77127544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821526928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1821526928
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2268636866
Short name T778
Test name
Test status
Simulation time 16575259722 ps
CPU time 17.43 seconds
Started Apr 15 12:26:54 PM PDT 24
Finished Apr 15 12:27:12 PM PDT 24
Peak memory 215444 kb
Host smart-83f5668a-5c66-4ee5-9352-23225febd1fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268636866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2268636866
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.508144188
Short name T793
Test name
Test status
Simulation time 3685507161 ps
CPU time 39.64 seconds
Started Apr 15 12:26:53 PM PDT 24
Finished Apr 15 12:27:33 PM PDT 24
Peak memory 207284 kb
Host smart-fab5e4d5-e81c-41f9-b19e-d3738b9e6d7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508144188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.508144188
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.99696431
Short name T32
Test name
Test status
Simulation time 270763341 ps
CPU time 1.17 seconds
Started Apr 15 12:26:47 PM PDT 24
Finished Apr 15 12:26:49 PM PDT 24
Peak memory 206992 kb
Host smart-ce6ef42d-9f7d-4905-be70-976c59f28a0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99696431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_
hw_reset.99696431
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2426390792
Short name T133
Test name
Test status
Simulation time 134084513 ps
CPU time 2.46 seconds
Started Apr 15 12:26:57 PM PDT 24
Finished Apr 15 12:27:00 PM PDT 24
Peak memory 216400 kb
Host smart-16e77177-112a-4911-befb-a0852fa05e22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426390792 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2426390792
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.192550040
Short name T844
Test name
Test status
Simulation time 181130611 ps
CPU time 2.68 seconds
Started Apr 15 12:26:46 PM PDT 24
Finished Apr 15 12:26:49 PM PDT 24
Peak memory 215296 kb
Host smart-33dd25f4-e624-44a1-b1f7-3b304fa3a5a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192550040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.192550040
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.510350341
Short name T781
Test name
Test status
Simulation time 17456142 ps
CPU time 0.78 seconds
Started Apr 15 12:26:50 PM PDT 24
Finished Apr 15 12:26:52 PM PDT 24
Peak memory 203360 kb
Host smart-0c07ce82-12df-4b01-ae1c-4368256d4092
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510350341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.510350341
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3464857041
Short name T145
Test name
Test status
Simulation time 63510238 ps
CPU time 1.31 seconds
Started Apr 15 12:26:49 PM PDT 24
Finished Apr 15 12:26:51 PM PDT 24
Peak memory 215256 kb
Host smart-06807edd-9ee2-42f3-965b-2471ec3da23d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464857041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3464857041
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1940904672
Short name T798
Test name
Test status
Simulation time 44412951 ps
CPU time 0.64 seconds
Started Apr 15 12:26:49 PM PDT 24
Finished Apr 15 12:26:50 PM PDT 24
Peak memory 203304 kb
Host smart-79953369-6ef7-4fb8-b1c1-d801578847cd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940904672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1940904672
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.224667762
Short name T761
Test name
Test status
Simulation time 79115127 ps
CPU time 1.96 seconds
Started Apr 15 12:26:54 PM PDT 24
Finished Apr 15 12:26:57 PM PDT 24
Peak memory 207052 kb
Host smart-7d083260-e077-4092-a86b-01824c536282
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224667762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.224667762
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3940950240
Short name T801
Test name
Test status
Simulation time 92909612 ps
CPU time 3.27 seconds
Started Apr 15 12:26:52 PM PDT 24
Finished Apr 15 12:26:56 PM PDT 24
Peak memory 215356 kb
Host smart-9fcdebca-e8c4-4b0d-9c42-abf24b4fd40e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940950240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
940950240
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1322407632
Short name T351
Test name
Test status
Simulation time 9282561647 ps
CPU time 20.49 seconds
Started Apr 15 12:26:48 PM PDT 24
Finished Apr 15 12:27:09 PM PDT 24
Peak memory 215412 kb
Host smart-b3c3c7d6-a24f-4cdb-b750-2f89e7efeac9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322407632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1322407632
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.826654568
Short name T759
Test name
Test status
Simulation time 11566059 ps
CPU time 0.75 seconds
Started Apr 15 12:27:26 PM PDT 24
Finished Apr 15 12:27:28 PM PDT 24
Peak memory 203612 kb
Host smart-9a246909-b961-4d44-a195-5d774e4945cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826654568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.826654568
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3558236270
Short name T748
Test name
Test status
Simulation time 13701963 ps
CPU time 0.7 seconds
Started Apr 15 12:27:25 PM PDT 24
Finished Apr 15 12:27:27 PM PDT 24
Peak memory 203224 kb
Host smart-cefc23fd-c9a3-4ec5-9c64-8fb5e7163708
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558236270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3558236270
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.34856364
Short name T745
Test name
Test status
Simulation time 51675866 ps
CPU time 0.69 seconds
Started Apr 15 12:27:23 PM PDT 24
Finished Apr 15 12:27:25 PM PDT 24
Peak memory 203340 kb
Host smart-bd567a80-3b60-4913-9cbc-1fb01f1f091c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34856364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.34856364
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2900722305
Short name T752
Test name
Test status
Simulation time 29938650 ps
CPU time 0.73 seconds
Started Apr 15 12:27:25 PM PDT 24
Finished Apr 15 12:27:26 PM PDT 24
Peak memory 203352 kb
Host smart-54e7b6d0-38af-40c1-9d32-31f84ee9a7e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900722305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2900722305
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3417257802
Short name T747
Test name
Test status
Simulation time 43947101 ps
CPU time 0.75 seconds
Started Apr 15 12:27:29 PM PDT 24
Finished Apr 15 12:27:30 PM PDT 24
Peak memory 203400 kb
Host smart-20350852-ebcd-4b9f-97ad-1b4cd116052f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417257802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3417257802
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2465535914
Short name T807
Test name
Test status
Simulation time 20946546 ps
CPU time 0.67 seconds
Started Apr 15 12:27:24 PM PDT 24
Finished Apr 15 12:27:25 PM PDT 24
Peak memory 203588 kb
Host smart-951e3624-32bb-4f51-9d2b-d07ec660cd28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465535914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2465535914
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1863702924
Short name T158
Test name
Test status
Simulation time 100950950 ps
CPU time 0.73 seconds
Started Apr 15 12:27:23 PM PDT 24
Finished Apr 15 12:27:24 PM PDT 24
Peak memory 203356 kb
Host smart-f1583009-5f33-4f6e-b3fb-1eed696a0ea4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863702924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1863702924
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4019268082
Short name T806
Test name
Test status
Simulation time 35985217 ps
CPU time 0.68 seconds
Started Apr 15 12:27:33 PM PDT 24
Finished Apr 15 12:27:35 PM PDT 24
Peak memory 203388 kb
Host smart-1a1bd561-88dd-4c10-9a57-f20d3748098e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019268082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4019268082
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1477349957
Short name T749
Test name
Test status
Simulation time 13578344 ps
CPU time 0.67 seconds
Started Apr 15 12:27:33 PM PDT 24
Finished Apr 15 12:27:34 PM PDT 24
Peak memory 203720 kb
Host smart-5dfe1184-0163-4b39-a3e2-529f26191ac1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477349957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1477349957
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.77203992
Short name T776
Test name
Test status
Simulation time 36728413 ps
CPU time 0.67 seconds
Started Apr 15 12:27:32 PM PDT 24
Finished Apr 15 12:27:34 PM PDT 24
Peak memory 203720 kb
Host smart-eac98f3a-0d32-486a-974b-ebd58546d29e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77203992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.77203992
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3458478993
Short name T802
Test name
Test status
Simulation time 216141924 ps
CPU time 15.12 seconds
Started Apr 15 12:26:59 PM PDT 24
Finished Apr 15 12:27:15 PM PDT 24
Peak memory 207100 kb
Host smart-68cc64bf-bd3f-4b5f-ab6f-47a07972683f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458478993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3458478993
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3002574222
Short name T828
Test name
Test status
Simulation time 190678147 ps
CPU time 11.46 seconds
Started Apr 15 12:27:03 PM PDT 24
Finished Apr 15 12:27:15 PM PDT 24
Peak memory 206996 kb
Host smart-cee4cf10-6667-42f0-aca6-102b9d4ae431
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002574222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3002574222
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.271608731
Short name T102
Test name
Test status
Simulation time 83093719 ps
CPU time 1.32 seconds
Started Apr 15 12:26:59 PM PDT 24
Finished Apr 15 12:27:01 PM PDT 24
Peak memory 215200 kb
Host smart-e3c4e7ae-110c-4831-860e-76854be0d014
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271608731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.271608731
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2284851778
Short name T795
Test name
Test status
Simulation time 104762143 ps
CPU time 1.58 seconds
Started Apr 15 12:27:01 PM PDT 24
Finished Apr 15 12:27:03 PM PDT 24
Peak memory 215360 kb
Host smart-3d2df8f3-8aa9-4692-8559-fdbdb68990f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284851778 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2284851778
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1138471753
Short name T144
Test name
Test status
Simulation time 34252253 ps
CPU time 1.21 seconds
Started Apr 15 12:27:00 PM PDT 24
Finished Apr 15 12:27:02 PM PDT 24
Peak memory 215280 kb
Host smart-a4a80cee-ebc5-4cb9-b156-01dbff19585c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138471753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
138471753
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1326400782
Short name T852
Test name
Test status
Simulation time 44224794 ps
CPU time 0.74 seconds
Started Apr 15 12:26:53 PM PDT 24
Finished Apr 15 12:26:54 PM PDT 24
Peak memory 203300 kb
Host smart-74795b35-8473-4cff-be48-a24d82d471b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326400782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
326400782
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4210694246
Short name T147
Test name
Test status
Simulation time 35544701 ps
CPU time 1.26 seconds
Started Apr 15 12:27:00 PM PDT 24
Finished Apr 15 12:27:02 PM PDT 24
Peak memory 215228 kb
Host smart-64b030f9-6a83-4e54-bf82-d5c0ef67aa24
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210694246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4210694246
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3002353434
Short name T803
Test name
Test status
Simulation time 17024117 ps
CPU time 0.69 seconds
Started Apr 15 12:26:53 PM PDT 24
Finished Apr 15 12:26:54 PM PDT 24
Peak memory 203652 kb
Host smart-ef724ce0-6138-49e8-b594-a1997c29ef15
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002353434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3002353434
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1859420767
Short name T766
Test name
Test status
Simulation time 215998230 ps
CPU time 3.47 seconds
Started Apr 15 12:26:59 PM PDT 24
Finished Apr 15 12:27:03 PM PDT 24
Peak memory 215140 kb
Host smart-9b9fc4bd-79a5-409a-b38c-b3fb381e49bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859420767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1859420767
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.122167624
Short name T814
Test name
Test status
Simulation time 130270428 ps
CPU time 1.29 seconds
Started Apr 15 12:26:54 PM PDT 24
Finished Apr 15 12:26:55 PM PDT 24
Peak memory 207124 kb
Host smart-1d4f7954-ca33-4d9a-8101-feec6df4ce13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122167624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.122167624
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4174184958
Short name T772
Test name
Test status
Simulation time 14880778 ps
CPU time 0.85 seconds
Started Apr 15 12:27:33 PM PDT 24
Finished Apr 15 12:27:35 PM PDT 24
Peak memory 203468 kb
Host smart-b13f6261-9e8e-4bff-94e0-b72143a27a59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174184958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
4174184958
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1931926800
Short name T840
Test name
Test status
Simulation time 12444544 ps
CPU time 0.73 seconds
Started Apr 15 12:27:27 PM PDT 24
Finished Apr 15 12:27:28 PM PDT 24
Peak memory 203352 kb
Host smart-fed2ff37-21a3-4d60-af0d-55e47847d85b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931926800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1931926800
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.757226617
Short name T856
Test name
Test status
Simulation time 14043057 ps
CPU time 0.71 seconds
Started Apr 15 12:27:33 PM PDT 24
Finished Apr 15 12:27:35 PM PDT 24
Peak memory 203732 kb
Host smart-1509339d-e174-4019-9989-b84bc121227e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757226617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.757226617
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2517850650
Short name T157
Test name
Test status
Simulation time 25697657 ps
CPU time 0.71 seconds
Started Apr 15 12:27:23 PM PDT 24
Finished Apr 15 12:27:24 PM PDT 24
Peak memory 203632 kb
Host smart-b1c2c3a6-e17e-4a0e-ad9e-89b3f198ddf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517850650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2517850650
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3553821362
Short name T777
Test name
Test status
Simulation time 16064151 ps
CPU time 0.78 seconds
Started Apr 15 12:27:25 PM PDT 24
Finished Apr 15 12:27:27 PM PDT 24
Peak memory 203628 kb
Host smart-fc8f16b8-014e-4917-9077-40bca948b5b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553821362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3553821362
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2274207774
Short name T829
Test name
Test status
Simulation time 12909077 ps
CPU time 0.69 seconds
Started Apr 15 12:27:24 PM PDT 24
Finished Apr 15 12:27:26 PM PDT 24
Peak memory 203612 kb
Host smart-b5c72db2-e0f1-4dd0-b0f1-58366efab215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274207774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2274207774
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3330799301
Short name T765
Test name
Test status
Simulation time 25582019 ps
CPU time 0.73 seconds
Started Apr 15 12:27:27 PM PDT 24
Finished Apr 15 12:27:28 PM PDT 24
Peak memory 203272 kb
Host smart-792d1022-813d-4913-87bc-9b1d1bf4dab4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330799301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3330799301
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1716809671
Short name T858
Test name
Test status
Simulation time 14839454 ps
CPU time 0.72 seconds
Started Apr 15 12:27:27 PM PDT 24
Finished Apr 15 12:27:28 PM PDT 24
Peak memory 203648 kb
Host smart-3ae5ef17-8900-4966-9d81-dd2cb87fac8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716809671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1716809671
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3433145388
Short name T758
Test name
Test status
Simulation time 72314374 ps
CPU time 0.71 seconds
Started Apr 15 12:27:29 PM PDT 24
Finished Apr 15 12:27:30 PM PDT 24
Peak memory 203316 kb
Host smart-a23d680a-84a7-486a-9d72-f5b2083d8c7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433145388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3433145388
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1532071657
Short name T832
Test name
Test status
Simulation time 43726614 ps
CPU time 0.7 seconds
Started Apr 15 12:27:32 PM PDT 24
Finished Apr 15 12:27:34 PM PDT 24
Peak memory 203452 kb
Host smart-964f128d-9d65-4183-b416-e577e87a1a85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532071657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1532071657
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.462995615
Short name T775
Test name
Test status
Simulation time 82974359 ps
CPU time 3.09 seconds
Started Apr 15 12:27:04 PM PDT 24
Finished Apr 15 12:27:07 PM PDT 24
Peak memory 216828 kb
Host smart-473495aa-4fa1-49cc-a9ec-dfe324447b89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462995615 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.462995615
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.680785369
Short name T136
Test name
Test status
Simulation time 253210655 ps
CPU time 1.38 seconds
Started Apr 15 12:27:05 PM PDT 24
Finished Apr 15 12:27:07 PM PDT 24
Peak memory 207084 kb
Host smart-c7f4ed49-1c78-4d61-a051-d7a2dda8542e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680785369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.680785369
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1542503812
Short name T831
Test name
Test status
Simulation time 15911843 ps
CPU time 0.69 seconds
Started Apr 15 12:27:04 PM PDT 24
Finished Apr 15 12:27:05 PM PDT 24
Peak memory 203312 kb
Host smart-e43e0b1f-aa97-4d8c-8d7e-6cf240106056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542503812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
542503812
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3243727943
Short name T788
Test name
Test status
Simulation time 604785165 ps
CPU time 2.88 seconds
Started Apr 15 12:27:07 PM PDT 24
Finished Apr 15 12:27:10 PM PDT 24
Peak memory 215296 kb
Host smart-4005bc3d-6244-465f-ba0c-feeb3e94669c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243727943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3243727943
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1496083159
Short name T348
Test name
Test status
Simulation time 388358954 ps
CPU time 3.98 seconds
Started Apr 15 12:27:00 PM PDT 24
Finished Apr 15 12:27:04 PM PDT 24
Peak memory 215336 kb
Host smart-62191d4f-0bb6-4c63-b05d-2bacd0ea46ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496083159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
496083159
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3751741519
Short name T352
Test name
Test status
Simulation time 1293712564 ps
CPU time 13.7 seconds
Started Apr 15 12:27:00 PM PDT 24
Finished Apr 15 12:27:15 PM PDT 24
Peak memory 215200 kb
Host smart-de94b780-da1e-4a63-9e09-69531d454277
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751741519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3751741519
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2772294974
Short name T827
Test name
Test status
Simulation time 97827579 ps
CPU time 3.18 seconds
Started Apr 15 12:27:05 PM PDT 24
Finished Apr 15 12:27:09 PM PDT 24
Peak memory 216772 kb
Host smart-bd884c84-cdf5-4502-a11a-19eec690f83e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772294974 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2772294974
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1672019349
Short name T842
Test name
Test status
Simulation time 35697253 ps
CPU time 1.22 seconds
Started Apr 15 12:27:04 PM PDT 24
Finished Apr 15 12:27:06 PM PDT 24
Peak memory 207052 kb
Host smart-50928909-aa68-4e81-9391-6cc20286f12f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672019349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
672019349
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2633862280
Short name T799
Test name
Test status
Simulation time 20123404 ps
CPU time 0.71 seconds
Started Apr 15 12:27:07 PM PDT 24
Finished Apr 15 12:27:08 PM PDT 24
Peak memory 203284 kb
Host smart-dce29585-5a73-492d-8e97-9507bfcadeba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633862280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
633862280
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4263523118
Short name T784
Test name
Test status
Simulation time 219769455 ps
CPU time 1.79 seconds
Started Apr 15 12:27:07 PM PDT 24
Finished Apr 15 12:27:10 PM PDT 24
Peak memory 215224 kb
Host smart-b680413f-6abe-416a-b80f-659d0309d8ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263523118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.4263523118
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4098803696
Short name T130
Test name
Test status
Simulation time 50284781 ps
CPU time 1.75 seconds
Started Apr 15 12:27:03 PM PDT 24
Finished Apr 15 12:27:06 PM PDT 24
Peak memory 215440 kb
Host smart-65366c0c-f2af-4bed-90bd-e54ed7c6b5c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098803696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
098803696
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3233158155
Short name T355
Test name
Test status
Simulation time 1156058061 ps
CPU time 17.88 seconds
Started Apr 15 12:27:07 PM PDT 24
Finished Apr 15 12:27:25 PM PDT 24
Peak memory 215448 kb
Host smart-e182d2ef-9d1c-4fa4-bc7c-d03a340cb270
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233158155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3233158155
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.978253241
Short name T770
Test name
Test status
Simulation time 681793170 ps
CPU time 3.62 seconds
Started Apr 15 12:27:07 PM PDT 24
Finished Apr 15 12:27:11 PM PDT 24
Peak memory 216296 kb
Host smart-aaf19cdd-8c8d-497e-84d2-86c4bd95220e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978253241 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.978253241
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3559177221
Short name T792
Test name
Test status
Simulation time 72531183 ps
CPU time 1.34 seconds
Started Apr 15 12:27:06 PM PDT 24
Finished Apr 15 12:27:08 PM PDT 24
Peak memory 207192 kb
Host smart-ad9519ea-c24d-48ec-aeb7-02c42928df05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559177221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
559177221
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3363073104
Short name T853
Test name
Test status
Simulation time 18005499 ps
CPU time 0.71 seconds
Started Apr 15 12:27:04 PM PDT 24
Finished Apr 15 12:27:05 PM PDT 24
Peak memory 203400 kb
Host smart-8c1606c5-4719-49c3-86b0-0a1975c25446
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363073104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
363073104
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3995142885
Short name T763
Test name
Test status
Simulation time 116042837 ps
CPU time 1.85 seconds
Started Apr 15 12:27:07 PM PDT 24
Finished Apr 15 12:27:10 PM PDT 24
Peak memory 215216 kb
Host smart-8d43ccc3-5790-4574-a262-93873ace1c84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995142885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3995142885
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2286794888
Short name T846
Test name
Test status
Simulation time 31042206 ps
CPU time 1.91 seconds
Started Apr 15 12:27:06 PM PDT 24
Finished Apr 15 12:27:08 PM PDT 24
Peak memory 215480 kb
Host smart-e34dda4b-526d-468f-a15f-dd7956f10141
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286794888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
286794888
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1255817052
Short name T132
Test name
Test status
Simulation time 4358551910 ps
CPU time 21.84 seconds
Started Apr 15 12:27:05 PM PDT 24
Finished Apr 15 12:27:27 PM PDT 24
Peak memory 215680 kb
Host smart-02480588-f227-4a56-9438-0c7da9cf249f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255817052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1255817052
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2790159323
Short name T109
Test name
Test status
Simulation time 55310151 ps
CPU time 3.8 seconds
Started Apr 15 12:27:16 PM PDT 24
Finished Apr 15 12:27:20 PM PDT 24
Peak memory 216948 kb
Host smart-7735c3b0-0c6f-4d0a-b5e4-b4919948c7f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790159323 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2790159323
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2051779080
Short name T822
Test name
Test status
Simulation time 72413333 ps
CPU time 1.95 seconds
Started Apr 15 12:27:11 PM PDT 24
Finished Apr 15 12:27:13 PM PDT 24
Peak memory 207072 kb
Host smart-79601f0c-9c13-49e0-9704-a0b009075476
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051779080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
051779080
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2851038702
Short name T812
Test name
Test status
Simulation time 48272438 ps
CPU time 0.77 seconds
Started Apr 15 12:27:11 PM PDT 24
Finished Apr 15 12:27:12 PM PDT 24
Peak memory 203368 kb
Host smart-fe6a54a0-6786-4194-948e-7776f2c504e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851038702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
851038702
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.233779198
Short name T789
Test name
Test status
Simulation time 277663960 ps
CPU time 2.61 seconds
Started Apr 15 12:27:09 PM PDT 24
Finished Apr 15 12:27:12 PM PDT 24
Peak memory 215192 kb
Host smart-542ace10-dc76-4fdd-91ca-27f484f830da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233779198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.233779198
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2599155235
Short name T815
Test name
Test status
Simulation time 111479893 ps
CPU time 2.23 seconds
Started Apr 15 12:27:03 PM PDT 24
Finished Apr 15 12:27:06 PM PDT 24
Peak memory 215372 kb
Host smart-8d6e0b59-d612-4fb4-a8bc-a8547254c187
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599155235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
599155235
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2193495603
Short name T131
Test name
Test status
Simulation time 10988312049 ps
CPU time 15.11 seconds
Started Apr 15 12:27:10 PM PDT 24
Finished Apr 15 12:27:25 PM PDT 24
Peak memory 215736 kb
Host smart-f16b259d-1a51-4b3a-a302-88a65010508e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193495603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2193495603
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1625512741
Short name T800
Test name
Test status
Simulation time 48662216 ps
CPU time 1.79 seconds
Started Apr 15 12:27:09 PM PDT 24
Finished Apr 15 12:27:12 PM PDT 24
Peak memory 215304 kb
Host smart-a40b1dee-59c7-4b4c-a965-3991abc0dcfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625512741 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1625512741
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2580925623
Short name T782
Test name
Test status
Simulation time 67536386 ps
CPU time 1.97 seconds
Started Apr 15 12:27:09 PM PDT 24
Finished Apr 15 12:27:11 PM PDT 24
Peak memory 207100 kb
Host smart-555072bf-b44f-45d8-8135-939b00a716a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580925623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
580925623
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2479201476
Short name T837
Test name
Test status
Simulation time 14211987 ps
CPU time 0.75 seconds
Started Apr 15 12:27:13 PM PDT 24
Finished Apr 15 12:27:14 PM PDT 24
Peak memory 203368 kb
Host smart-4b3c152a-51f0-413d-bd30-80c60087d7be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479201476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
479201476
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.58687642
Short name T783
Test name
Test status
Simulation time 117080756 ps
CPU time 1.87 seconds
Started Apr 15 12:27:10 PM PDT 24
Finished Apr 15 12:27:12 PM PDT 24
Peak memory 215208 kb
Host smart-7e6257b1-af7a-42d7-957f-f39946a861f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58687642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi
_device_same_csr_outstanding.58687642
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.237796919
Short name T805
Test name
Test status
Simulation time 904980515 ps
CPU time 2.42 seconds
Started Apr 15 12:27:11 PM PDT 24
Finished Apr 15 12:27:14 PM PDT 24
Peak memory 215376 kb
Host smart-425b5cde-5dab-4701-9ef8-d70083894cda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237796919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.237796919
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2353895683
Short name T110
Test name
Test status
Simulation time 1360760647 ps
CPU time 12.35 seconds
Started Apr 15 12:27:12 PM PDT 24
Finished Apr 15 12:27:25 PM PDT 24
Peak memory 215200 kb
Host smart-d1dee9dd-9a4b-4034-8cc4-f09fded59be2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353895683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2353895683
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1200638122
Short name T537
Test name
Test status
Simulation time 25706466 ps
CPU time 0.74 seconds
Started Apr 15 01:22:31 PM PDT 24
Finished Apr 15 01:22:32 PM PDT 24
Peak memory 205704 kb
Host smart-1afa1dd0-b189-4699-aea7-5aa7e13bf9af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200638122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
200638122
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2806440440
Short name T423
Test name
Test status
Simulation time 24052539 ps
CPU time 0.87 seconds
Started Apr 15 01:22:19 PM PDT 24
Finished Apr 15 01:22:20 PM PDT 24
Peak memory 206656 kb
Host smart-0ea834f4-a02b-43bf-94ae-be957681ad43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806440440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2806440440
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2277344926
Short name T550
Test name
Test status
Simulation time 52836932 ps
CPU time 1.2 seconds
Started Apr 15 01:22:20 PM PDT 24
Finished Apr 15 01:22:22 PM PDT 24
Peak memory 216980 kb
Host smart-c337d651-c7df-49bc-8d12-e1c770e43d03
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277344926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2277344926
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1008121537
Short name T322
Test name
Test status
Simulation time 2007179753 ps
CPU time 7.63 seconds
Started Apr 15 01:22:18 PM PDT 24
Finished Apr 15 01:22:26 PM PDT 24
Peak memory 223016 kb
Host smart-cb9a49b0-eb35-4ade-89e2-dbc29bb415b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008121537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1008121537
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3997507826
Short name T673
Test name
Test status
Simulation time 1421305225 ps
CPU time 4.88 seconds
Started Apr 15 01:22:22 PM PDT 24
Finished Apr 15 01:22:27 PM PDT 24
Peak memory 220756 kb
Host smart-d32a59de-0797-43b4-a45e-1987f831ca30
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3997507826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3997507826
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3142094967
Short name T488
Test name
Test status
Simulation time 742542627 ps
CPU time 7.46 seconds
Started Apr 15 01:22:19 PM PDT 24
Finished Apr 15 01:22:27 PM PDT 24
Peak memory 216560 kb
Host smart-8e4da0be-1d84-4017-8bee-d227b9be4dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142094967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3142094967
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1875416310
Short name T448
Test name
Test status
Simulation time 7373258059 ps
CPU time 19.9 seconds
Started Apr 15 01:22:20 PM PDT 24
Finished Apr 15 01:22:40 PM PDT 24
Peak memory 216548 kb
Host smart-adc2d033-07e0-41fd-ba8e-e6161c52a68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875416310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1875416310
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3395661696
Short name T601
Test name
Test status
Simulation time 144125162 ps
CPU time 1.52 seconds
Started Apr 15 01:22:17 PM PDT 24
Finished Apr 15 01:22:19 PM PDT 24
Peak memory 216412 kb
Host smart-372d2459-7214-4270-865a-a3abb38f8e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395661696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3395661696
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2320875945
Short name T548
Test name
Test status
Simulation time 116748364 ps
CPU time 0.94 seconds
Started Apr 15 01:22:18 PM PDT 24
Finished Apr 15 01:22:19 PM PDT 24
Peak memory 206884 kb
Host smart-4aa8d495-417e-4a2a-9681-2b5a3750223c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320875945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2320875945
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2458885780
Short name T658
Test name
Test status
Simulation time 20563775 ps
CPU time 0.68 seconds
Started Apr 15 01:22:38 PM PDT 24
Finished Apr 15 01:22:39 PM PDT 24
Peak memory 204772 kb
Host smart-b0570135-6f71-4312-962c-3446922a25c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458885780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
458885780
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3763978679
Short name T510
Test name
Test status
Simulation time 20760863 ps
CPU time 0.79 seconds
Started Apr 15 01:22:28 PM PDT 24
Finished Apr 15 01:22:29 PM PDT 24
Peak memory 206960 kb
Host smart-2da18ff6-91f4-4edd-a323-0300d937e904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763978679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3763978679
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.510483488
Short name T626
Test name
Test status
Simulation time 403331433 ps
CPU time 13.01 seconds
Started Apr 15 01:22:35 PM PDT 24
Finished Apr 15 01:22:49 PM PDT 24
Peak memory 250132 kb
Host smart-57679c28-d8ef-4c49-9ba9-fc4be4c64343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510483488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.510483488
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3343501660
Short name T317
Test name
Test status
Simulation time 1447909502 ps
CPU time 13.72 seconds
Started Apr 15 01:22:30 PM PDT 24
Finished Apr 15 01:22:44 PM PDT 24
Peak memory 223588 kb
Host smart-5823993a-8fbe-43a5-abeb-c9f4d9d89522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343501660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3343501660
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2373258730
Short name T455
Test name
Test status
Simulation time 155145372 ps
CPU time 4 seconds
Started Apr 15 01:22:32 PM PDT 24
Finished Apr 15 01:22:36 PM PDT 24
Peak memory 219492 kb
Host smart-552a8506-f7b5-4935-8f43-d38211da3812
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2373258730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2373258730
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2355332814
Short name T44
Test name
Test status
Simulation time 1161981772 ps
CPU time 1.13 seconds
Started Apr 15 01:22:38 PM PDT 24
Finished Apr 15 01:22:40 PM PDT 24
Peak memory 236736 kb
Host smart-82a5d34d-ce06-43f3-a49a-b3b8dc3097bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355332814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2355332814
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.4188034951
Short name T474
Test name
Test status
Simulation time 536736935 ps
CPU time 3.18 seconds
Started Apr 15 01:22:28 PM PDT 24
Finished Apr 15 01:22:31 PM PDT 24
Peak memory 216588 kb
Host smart-3a67e5ea-d402-4f31-8a2d-cfdbdc06f82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188034951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4188034951
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1410813757
Short name T431
Test name
Test status
Simulation time 1450685224 ps
CPU time 8.52 seconds
Started Apr 15 01:22:26 PM PDT 24
Finished Apr 15 01:22:35 PM PDT 24
Peak memory 216572 kb
Host smart-e7822dc6-1fba-429e-bc99-51c33b55b9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410813757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1410813757
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.481263710
Short name T543
Test name
Test status
Simulation time 203406052 ps
CPU time 3.7 seconds
Started Apr 15 01:22:28 PM PDT 24
Finished Apr 15 01:22:32 PM PDT 24
Peak memory 216680 kb
Host smart-cae6ee86-b90e-42cf-a6c6-4fb34a2df589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481263710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.481263710
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3329121808
Short name T445
Test name
Test status
Simulation time 148181762 ps
CPU time 1.12 seconds
Started Apr 15 01:22:31 PM PDT 24
Finished Apr 15 01:22:32 PM PDT 24
Peak memory 206912 kb
Host smart-8f739943-1b8c-4455-8245-ee47adb1042a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329121808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3329121808
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1621559094
Short name T306
Test name
Test status
Simulation time 10530310592 ps
CPU time 28 seconds
Started Apr 15 01:22:33 PM PDT 24
Finished Apr 15 01:23:02 PM PDT 24
Peak memory 216572 kb
Host smart-0762dd72-601e-41ae-8d5f-2c9d04af9c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621559094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1621559094
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.346176821
Short name T656
Test name
Test status
Simulation time 21079187 ps
CPU time 0.69 seconds
Started Apr 15 01:23:40 PM PDT 24
Finished Apr 15 01:23:41 PM PDT 24
Peak memory 204820 kb
Host smart-c4995f8d-01a3-4dd7-a2f7-906bfdb2de15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346176821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.346176821
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3244839412
Short name T491
Test name
Test status
Simulation time 55393859 ps
CPU time 0.77 seconds
Started Apr 15 01:23:37 PM PDT 24
Finished Apr 15 01:23:38 PM PDT 24
Peak memory 206628 kb
Host smart-ff99d7f8-081b-47a3-abab-399a532dd33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244839412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3244839412
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1148683234
Short name T531
Test name
Test status
Simulation time 549103093 ps
CPU time 20.69 seconds
Started Apr 15 01:23:41 PM PDT 24
Finished Apr 15 01:24:02 PM PDT 24
Peak memory 249408 kb
Host smart-c43d2bde-8dc6-468f-9ef4-e50d772ce293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148683234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1148683234
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2477974802
Short name T4
Test name
Test status
Simulation time 2314833991 ps
CPU time 13.22 seconds
Started Apr 15 01:23:36 PM PDT 24
Finished Apr 15 01:23:49 PM PDT 24
Peak memory 217096 kb
Host smart-74103029-cea3-48c8-a7f7-1bf0708d1f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477974802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2477974802
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2068905807
Short name T501
Test name
Test status
Simulation time 29801744 ps
CPU time 1.11 seconds
Started Apr 15 01:23:36 PM PDT 24
Finished Apr 15 01:23:37 PM PDT 24
Peak memory 216976 kb
Host smart-e8116668-dd47-417a-8856-f0d4061ac874
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068905807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2068905807
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3085893251
Short name T523
Test name
Test status
Simulation time 2909181058 ps
CPU time 30.5 seconds
Started Apr 15 01:23:36 PM PDT 24
Finished Apr 15 01:24:07 PM PDT 24
Peak memory 216680 kb
Host smart-583d937d-6111-4356-bff7-f821022013a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085893251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3085893251
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3796101825
Short name T460
Test name
Test status
Simulation time 1068917997 ps
CPU time 4.82 seconds
Started Apr 15 01:23:35 PM PDT 24
Finished Apr 15 01:23:40 PM PDT 24
Peak memory 216380 kb
Host smart-75c57e68-776c-4c76-a017-49b0cf8c4678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796101825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3796101825
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.410307625
Short name T516
Test name
Test status
Simulation time 51092206 ps
CPU time 3.05 seconds
Started Apr 15 01:23:35 PM PDT 24
Finished Apr 15 01:23:39 PM PDT 24
Peak memory 216528 kb
Host smart-8723cd1b-05e1-4855-925f-df4fe405a2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410307625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.410307625
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1592812509
Short name T457
Test name
Test status
Simulation time 47756416 ps
CPU time 0.8 seconds
Started Apr 15 01:23:36 PM PDT 24
Finished Apr 15 01:23:37 PM PDT 24
Peak memory 205808 kb
Host smart-4d1169c9-ffba-494c-aa51-10791496f437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592812509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1592812509
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3546217204
Short name T241
Test name
Test status
Simulation time 7557761989 ps
CPU time 3.99 seconds
Started Apr 15 01:23:36 PM PDT 24
Finished Apr 15 01:23:40 PM PDT 24
Peak memory 222240 kb
Host smart-e535facb-978e-4a52-931e-0b9117f2972d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546217204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3546217204
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3536839203
Short name T451
Test name
Test status
Simulation time 148021066 ps
CPU time 0.74 seconds
Started Apr 15 01:23:48 PM PDT 24
Finished Apr 15 01:23:49 PM PDT 24
Peak memory 204844 kb
Host smart-815391fb-221d-4a41-86ff-a2c4f8c22cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536839203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3536839203
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2715283190
Short name T740
Test name
Test status
Simulation time 72881241 ps
CPU time 0.77 seconds
Started Apr 15 01:23:40 PM PDT 24
Finished Apr 15 01:23:41 PM PDT 24
Peak memory 206636 kb
Host smart-8b1e0b39-b748-4be5-9d25-3058869bb74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715283190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2715283190
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3112188185
Short name T99
Test name
Test status
Simulation time 5154417598 ps
CPU time 63.61 seconds
Started Apr 15 01:23:47 PM PDT 24
Finished Apr 15 01:24:51 PM PDT 24
Peak memory 239104 kb
Host smart-b7cb7b28-c126-4fde-9540-4e80ac5882e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112188185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3112188185
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.4106942291
Short name T726
Test name
Test status
Simulation time 16158674 ps
CPU time 0.97 seconds
Started Apr 15 01:23:44 PM PDT 24
Finished Apr 15 01:23:46 PM PDT 24
Peak memory 218164 kb
Host smart-6774b2bb-2391-4da3-92e8-51877fc76feb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106942291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.4106942291
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3209591841
Short name T605
Test name
Test status
Simulation time 14378544373 ps
CPU time 13.12 seconds
Started Apr 15 01:23:48 PM PDT 24
Finished Apr 15 01:24:01 PM PDT 24
Peak memory 219060 kb
Host smart-aac506b3-0134-450c-a02e-f8bbb6da055f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3209591841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3209591841
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.15198605
Short name T625
Test name
Test status
Simulation time 2228659249 ps
CPU time 34.62 seconds
Started Apr 15 01:23:44 PM PDT 24
Finished Apr 15 01:24:19 PM PDT 24
Peak memory 216648 kb
Host smart-aea1b7eb-2634-48cb-a060-373f45d2663b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15198605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.15198605
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.938133329
Short name T443
Test name
Test status
Simulation time 7723455491 ps
CPU time 12.22 seconds
Started Apr 15 01:23:45 PM PDT 24
Finished Apr 15 01:23:58 PM PDT 24
Peak memory 216652 kb
Host smart-43cffa72-109b-4e96-899b-ee7c72f33e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938133329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.938133329
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2217175840
Short name T679
Test name
Test status
Simulation time 1208000307 ps
CPU time 8.18 seconds
Started Apr 15 01:23:44 PM PDT 24
Finished Apr 15 01:23:52 PM PDT 24
Peak memory 216564 kb
Host smart-5875df8a-63a7-455a-aa6a-fc7fd777e32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217175840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2217175840
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1827017002
Short name T487
Test name
Test status
Simulation time 297769769 ps
CPU time 0.99 seconds
Started Apr 15 01:23:44 PM PDT 24
Finished Apr 15 01:23:46 PM PDT 24
Peak memory 205872 kb
Host smart-7cea86c2-a04b-42ea-ac70-93dbebb9e7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827017002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1827017002
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1293666828
Short name T608
Test name
Test status
Simulation time 23584646 ps
CPU time 0.68 seconds
Started Apr 15 01:24:05 PM PDT 24
Finished Apr 15 01:24:06 PM PDT 24
Peak memory 205440 kb
Host smart-4a364284-71f2-4f44-8a18-54bd3595e95a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293666828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1293666828
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1356455745
Short name T439
Test name
Test status
Simulation time 36674339 ps
CPU time 0.73 seconds
Started Apr 15 01:23:48 PM PDT 24
Finished Apr 15 01:23:49 PM PDT 24
Peak memory 206972 kb
Host smart-976380cc-9c56-4976-984b-21f75fed27f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356455745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1356455745
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1557183676
Short name T728
Test name
Test status
Simulation time 2450788915 ps
CPU time 8.46 seconds
Started Apr 15 01:24:05 PM PDT 24
Finished Apr 15 01:24:14 PM PDT 24
Peak memory 233008 kb
Host smart-2509fe40-7ab7-480b-94cb-8458dff1a506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557183676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1557183676
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3550741898
Short name T266
Test name
Test status
Simulation time 1185939067 ps
CPU time 5.72 seconds
Started Apr 15 01:23:54 PM PDT 24
Finished Apr 15 01:24:00 PM PDT 24
Peak memory 219312 kb
Host smart-8a83a06f-ec20-4fac-8150-598109fc51ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550741898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3550741898
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2561916792
Short name T553
Test name
Test status
Simulation time 46429634 ps
CPU time 1.07 seconds
Started Apr 15 01:23:47 PM PDT 24
Finished Apr 15 01:23:49 PM PDT 24
Peak memory 218216 kb
Host smart-5735adf5-787c-41a4-94aa-81720f77cb8d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561916792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2561916792
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1970144694
Short name T302
Test name
Test status
Simulation time 4594938737 ps
CPU time 10.09 seconds
Started Apr 15 01:23:55 PM PDT 24
Finished Apr 15 01:24:06 PM PDT 24
Peak memory 221220 kb
Host smart-f7bf297d-d72a-4b33-b96c-24b0b105ab61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970144694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1970144694
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1553856582
Short name T48
Test name
Test status
Simulation time 576691430 ps
CPU time 7.98 seconds
Started Apr 15 01:24:05 PM PDT 24
Finished Apr 15 01:24:14 PM PDT 24
Peak memory 218796 kb
Host smart-283b939b-4325-4189-b2c7-e788983c45e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1553856582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1553856582
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3090443741
Short name T710
Test name
Test status
Simulation time 93242448 ps
CPU time 1.43 seconds
Started Apr 15 01:23:51 PM PDT 24
Finished Apr 15 01:23:53 PM PDT 24
Peak memory 216616 kb
Host smart-b6f35540-411c-4e38-b502-0feddeef2f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090443741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3090443741
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3959269749
Short name T577
Test name
Test status
Simulation time 74503349 ps
CPU time 0.85 seconds
Started Apr 15 01:23:54 PM PDT 24
Finished Apr 15 01:23:56 PM PDT 24
Peak memory 206896 kb
Host smart-60f3dc7b-021e-4983-bc39-6e499dd1ea0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959269749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3959269749
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3395511587
Short name T207
Test name
Test status
Simulation time 1628982683 ps
CPU time 6.44 seconds
Started Apr 15 01:23:53 PM PDT 24
Finished Apr 15 01:24:00 PM PDT 24
Peak memory 216552 kb
Host smart-67da9bc2-64c8-41ea-a7ba-be7daa45074b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395511587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3395511587
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1974802137
Short name T505
Test name
Test status
Simulation time 13964493 ps
CPU time 0.71 seconds
Started Apr 15 01:24:04 PM PDT 24
Finished Apr 15 01:24:05 PM PDT 24
Peak memory 205380 kb
Host smart-f08457af-820c-4a69-8ad5-5a97f9348ba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974802137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1974802137
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1037303268
Short name T24
Test name
Test status
Simulation time 354652979 ps
CPU time 3.26 seconds
Started Apr 15 01:24:00 PM PDT 24
Finished Apr 15 01:24:04 PM PDT 24
Peak memory 223516 kb
Host smart-a224b047-dc49-4377-91a8-832a80669487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037303268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1037303268
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2609202444
Short name T475
Test name
Test status
Simulation time 53606760 ps
CPU time 0.74 seconds
Started Apr 15 01:24:05 PM PDT 24
Finished Apr 15 01:24:07 PM PDT 24
Peak memory 206636 kb
Host smart-21f9aa17-00c9-47af-b43a-865909b96825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609202444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2609202444
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2561169714
Short name T732
Test name
Test status
Simulation time 7210760445 ps
CPU time 55.07 seconds
Started Apr 15 01:24:04 PM PDT 24
Finished Apr 15 01:25:00 PM PDT 24
Peak memory 254836 kb
Host smart-7299ca15-08fb-4834-97c4-b618eff31ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561169714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2561169714
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2765469658
Short name T208
Test name
Test status
Simulation time 12369389927 ps
CPU time 12.08 seconds
Started Apr 15 01:24:00 PM PDT 24
Finished Apr 15 01:24:12 PM PDT 24
Peak memory 216900 kb
Host smart-1fc055e9-b742-4d82-9248-c34fce512c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765469658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2765469658
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2540686491
Short name T497
Test name
Test status
Simulation time 109213560 ps
CPU time 1.01 seconds
Started Apr 15 01:24:05 PM PDT 24
Finished Apr 15 01:24:07 PM PDT 24
Peak memory 218192 kb
Host smart-3dba3abf-0569-458a-b00e-5da864ce8768
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540686491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2540686491
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1575513353
Short name T52
Test name
Test status
Simulation time 608540514 ps
CPU time 3.77 seconds
Started Apr 15 01:24:00 PM PDT 24
Finished Apr 15 01:24:04 PM PDT 24
Peak memory 216908 kb
Host smart-e9345186-d532-49bb-adcf-1e68c958d07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575513353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1575513353
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.4180590591
Short name T742
Test name
Test status
Simulation time 1243482055 ps
CPU time 8.23 seconds
Started Apr 15 01:24:05 PM PDT 24
Finished Apr 15 01:24:14 PM PDT 24
Peak memory 222024 kb
Host smart-c496fe64-794d-4254-9076-06606dfe8c70
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4180590591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.4180590591
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.823488422
Short name T623
Test name
Test status
Simulation time 690278459 ps
CPU time 2.68 seconds
Started Apr 15 01:24:00 PM PDT 24
Finished Apr 15 01:24:03 PM PDT 24
Peak memory 207976 kb
Host smart-eb28aa62-78e3-4896-9f1d-21e3add99b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823488422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.823488422
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3038215537
Short name T613
Test name
Test status
Simulation time 254713371 ps
CPU time 0.88 seconds
Started Apr 15 01:24:00 PM PDT 24
Finished Apr 15 01:24:02 PM PDT 24
Peak memory 206908 kb
Host smart-c0d58e3a-82ad-487d-a301-ea368cfa91be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038215537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3038215537
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3405137626
Short name T217
Test name
Test status
Simulation time 5153998681 ps
CPU time 15.9 seconds
Started Apr 15 01:24:01 PM PDT 24
Finished Apr 15 01:24:17 PM PDT 24
Peak memory 239548 kb
Host smart-8e2c3d70-d168-4a47-9fbb-83448a80e86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405137626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3405137626
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3362395147
Short name T698
Test name
Test status
Simulation time 12953151 ps
CPU time 0.69 seconds
Started Apr 15 01:24:12 PM PDT 24
Finished Apr 15 01:24:13 PM PDT 24
Peak memory 205124 kb
Host smart-876a0c04-ac98-4d69-bcde-faba36791c56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362395147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3362395147
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2598714767
Short name T459
Test name
Test status
Simulation time 12673369 ps
CPU time 0.74 seconds
Started Apr 15 01:24:04 PM PDT 24
Finished Apr 15 01:24:05 PM PDT 24
Peak memory 205632 kb
Host smart-c089c7c3-3447-431e-96ba-93e23ce8183e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598714767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2598714767
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.152564486
Short name T188
Test name
Test status
Simulation time 575090473 ps
CPU time 12.46 seconds
Started Apr 15 01:24:16 PM PDT 24
Finished Apr 15 01:24:28 PM PDT 24
Peak memory 236152 kb
Host smart-f4edff80-898f-4757-93c3-e679a53f2bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152564486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.152564486
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2262566109
Short name T719
Test name
Test status
Simulation time 27698428 ps
CPU time 0.99 seconds
Started Apr 15 01:24:08 PM PDT 24
Finished Apr 15 01:24:10 PM PDT 24
Peak memory 216972 kb
Host smart-38a24042-37d6-4c0a-be59-ac5a12783eed
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262566109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2262566109
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1616015507
Short name T628
Test name
Test status
Simulation time 849082973 ps
CPU time 4.72 seconds
Started Apr 15 01:24:11 PM PDT 24
Finished Apr 15 01:24:16 PM PDT 24
Peak memory 222416 kb
Host smart-7834de51-debc-4375-922c-c28705130d8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1616015507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1616015507
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3227936878
Short name T22
Test name
Test status
Simulation time 54968335 ps
CPU time 1.01 seconds
Started Apr 15 01:24:12 PM PDT 24
Finished Apr 15 01:24:14 PM PDT 24
Peak memory 207052 kb
Host smart-5f74f660-823d-43fe-90d0-00979b476e1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227936878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3227936878
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.81040879
Short name T580
Test name
Test status
Simulation time 35842166893 ps
CPU time 48.21 seconds
Started Apr 15 01:24:09 PM PDT 24
Finished Apr 15 01:24:58 PM PDT 24
Peak memory 216652 kb
Host smart-81c03cd0-9aec-415d-b8e7-9258c14b6ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81040879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.81040879
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1399333150
Short name T525
Test name
Test status
Simulation time 1063938860 ps
CPU time 6.85 seconds
Started Apr 15 01:24:08 PM PDT 24
Finished Apr 15 01:24:15 PM PDT 24
Peak memory 216596 kb
Host smart-00eeafb6-c806-4d69-8f5f-73e636d7e920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399333150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1399333150
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3900394241
Short name T435
Test name
Test status
Simulation time 163739100 ps
CPU time 1.13 seconds
Started Apr 15 01:24:08 PM PDT 24
Finished Apr 15 01:24:09 PM PDT 24
Peak memory 207092 kb
Host smart-89d845a8-b3c9-4c60-b05b-9aee08a90c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900394241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3900394241
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.432752173
Short name T666
Test name
Test status
Simulation time 95409061 ps
CPU time 0.78 seconds
Started Apr 15 01:24:09 PM PDT 24
Finished Apr 15 01:24:10 PM PDT 24
Peak memory 205860 kb
Host smart-1ee312e9-e8fe-4e5b-80aa-86d974fdcc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432752173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.432752173
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1245512519
Short name T551
Test name
Test status
Simulation time 54141581 ps
CPU time 0.73 seconds
Started Apr 15 01:24:19 PM PDT 24
Finished Apr 15 01:24:20 PM PDT 24
Peak memory 205392 kb
Host smart-e19cf463-a180-461a-87ce-dab16216758c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245512519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1245512519
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2546761768
Short name T500
Test name
Test status
Simulation time 90557815 ps
CPU time 0.79 seconds
Started Apr 15 01:24:11 PM PDT 24
Finished Apr 15 01:24:12 PM PDT 24
Peak memory 206652 kb
Host smart-a7a677c6-dca5-456d-9023-bfb0e43e3787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546761768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2546761768
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3228674618
Short name T660
Test name
Test status
Simulation time 7227626696 ps
CPU time 77.81 seconds
Started Apr 15 01:24:20 PM PDT 24
Finished Apr 15 01:25:38 PM PDT 24
Peak memory 233020 kb
Host smart-41ffe404-148c-4a55-a172-0e5934d388d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228674618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3228674618
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1005874445
Short name T264
Test name
Test status
Simulation time 605483810 ps
CPU time 7.57 seconds
Started Apr 15 01:24:17 PM PDT 24
Finished Apr 15 01:24:25 PM PDT 24
Peak memory 217104 kb
Host smart-0a238e2f-8bc9-47d3-a34d-473494141064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005874445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1005874445
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3593646835
Short name T45
Test name
Test status
Simulation time 140160114 ps
CPU time 1.05 seconds
Started Apr 15 01:24:13 PM PDT 24
Finished Apr 15 01:24:15 PM PDT 24
Peak memory 216956 kb
Host smart-49a54155-79db-4a29-ab48-07db9fec6842
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593646835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3593646835
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2683996092
Short name T154
Test name
Test status
Simulation time 1170810467 ps
CPU time 7.73 seconds
Started Apr 15 01:24:20 PM PDT 24
Finished Apr 15 01:24:28 PM PDT 24
Peak memory 218960 kb
Host smart-042609b2-36ef-45b7-a033-ca27bea397f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2683996092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2683996092
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2795145107
Short name T541
Test name
Test status
Simulation time 7830879561 ps
CPU time 40.18 seconds
Started Apr 15 01:24:17 PM PDT 24
Finished Apr 15 01:24:57 PM PDT 24
Peak memory 221036 kb
Host smart-cc0f6c31-9d6b-4a89-aa01-54db406bcc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795145107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2795145107
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1067751340
Short name T547
Test name
Test status
Simulation time 7412421937 ps
CPU time 5.02 seconds
Started Apr 15 01:24:13 PM PDT 24
Finished Apr 15 01:24:18 PM PDT 24
Peak memory 216512 kb
Host smart-3e71f233-d6f9-477c-928f-aa96f002fc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067751340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1067751340
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.652875236
Short name T642
Test name
Test status
Simulation time 194512155 ps
CPU time 5.62 seconds
Started Apr 15 01:24:17 PM PDT 24
Finished Apr 15 01:24:23 PM PDT 24
Peak memory 216684 kb
Host smart-8fd34a0b-2d92-4e94-afa9-205525889713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652875236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.652875236
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.976303401
Short name T529
Test name
Test status
Simulation time 44421760 ps
CPU time 0.79 seconds
Started Apr 15 01:24:16 PM PDT 24
Finished Apr 15 01:24:17 PM PDT 24
Peak memory 205876 kb
Host smart-a43d7395-ef8a-4c78-9bf1-945ea65bd188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976303401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.976303401
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1505485528
Short name T538
Test name
Test status
Simulation time 14518848 ps
CPU time 0.74 seconds
Started Apr 15 01:24:33 PM PDT 24
Finished Apr 15 01:24:34 PM PDT 24
Peak memory 205416 kb
Host smart-9dcc793d-641c-4d7f-8e7a-6fddc7bb726e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505485528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1505485528
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2475283558
Short name T630
Test name
Test status
Simulation time 61786629 ps
CPU time 0.75 seconds
Started Apr 15 01:24:27 PM PDT 24
Finished Apr 15 01:24:28 PM PDT 24
Peak memory 205960 kb
Host smart-cc6764dc-c327-4ab4-8bfd-aa2b2f4f12a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475283558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2475283558
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1296552096
Short name T294
Test name
Test status
Simulation time 13229130077 ps
CPU time 48.55 seconds
Started Apr 15 01:24:30 PM PDT 24
Finished Apr 15 01:25:19 PM PDT 24
Peak memory 241220 kb
Host smart-0a68a5ed-626e-47b3-a6fc-9543dedb38c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296552096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1296552096
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3579090606
Short name T249
Test name
Test status
Simulation time 223540625 ps
CPU time 4.94 seconds
Started Apr 15 01:24:28 PM PDT 24
Finished Apr 15 01:24:33 PM PDT 24
Peak memory 223228 kb
Host smart-1e8a374f-b9a4-45b7-8e87-ee1d2282b6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579090606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3579090606
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2051746621
Short name T712
Test name
Test status
Simulation time 15664540 ps
CPU time 1.01 seconds
Started Apr 15 01:24:25 PM PDT 24
Finished Apr 15 01:24:26 PM PDT 24
Peak memory 216980 kb
Host smart-e5933b5a-f106-4657-83e1-bc337a6425e7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051746621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2051746621
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3841856020
Short name T203
Test name
Test status
Simulation time 18872090667 ps
CPU time 15.06 seconds
Started Apr 15 01:24:24 PM PDT 24
Finished Apr 15 01:24:40 PM PDT 24
Peak memory 233048 kb
Host smart-3a08a9d5-2b02-436d-8d3d-20525e0f7c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841856020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3841856020
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1753871810
Short name T107
Test name
Test status
Simulation time 2078721863 ps
CPU time 12.44 seconds
Started Apr 15 01:24:29 PM PDT 24
Finished Apr 15 01:24:42 PM PDT 24
Peak memory 220168 kb
Host smart-b02a754e-ba0b-4b2f-b81d-82ecca04cc76
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1753871810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1753871810
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2867253674
Short name T391
Test name
Test status
Simulation time 3148482807 ps
CPU time 26.76 seconds
Started Apr 15 01:24:27 PM PDT 24
Finished Apr 15 01:24:54 PM PDT 24
Peak memory 216604 kb
Host smart-ee05c4e0-b1cb-41d3-b1fd-fcf6756b43c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867253674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2867253674
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.569619294
Short name T606
Test name
Test status
Simulation time 9014375344 ps
CPU time 10.6 seconds
Started Apr 15 01:24:25 PM PDT 24
Finished Apr 15 01:24:36 PM PDT 24
Peak memory 216636 kb
Host smart-1e545331-c3c3-4e8a-b957-acaa45b80946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569619294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.569619294
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3706909535
Short name T581
Test name
Test status
Simulation time 56629071 ps
CPU time 1.48 seconds
Started Apr 15 01:24:24 PM PDT 24
Finished Apr 15 01:24:26 PM PDT 24
Peak memory 216440 kb
Host smart-7ac3b965-2556-4de4-a4a0-2d40e0a2ecda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706909535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3706909535
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1840594190
Short name T676
Test name
Test status
Simulation time 86268583 ps
CPU time 0.97 seconds
Started Apr 15 01:24:25 PM PDT 24
Finished Apr 15 01:24:26 PM PDT 24
Peak memory 206044 kb
Host smart-353f81bc-4f10-4c56-b458-b25f8454dc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840594190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1840594190
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1828065780
Short name T672
Test name
Test status
Simulation time 36896048 ps
CPU time 0.69 seconds
Started Apr 15 01:24:43 PM PDT 24
Finished Apr 15 01:24:44 PM PDT 24
Peak memory 205740 kb
Host smart-abd83a3e-3356-4dda-a26a-48bef2b1bbe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828065780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1828065780
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2387346158
Short name T441
Test name
Test status
Simulation time 18214086 ps
CPU time 0.77 seconds
Started Apr 15 01:24:33 PM PDT 24
Finished Apr 15 01:24:34 PM PDT 24
Peak memory 206984 kb
Host smart-4c79296f-ccb9-4cb1-b30b-acd76efc7dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387346158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2387346158
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.605104049
Short name T357
Test name
Test status
Simulation time 27918108758 ps
CPU time 79.24 seconds
Started Apr 15 01:24:39 PM PDT 24
Finished Apr 15 01:25:59 PM PDT 24
Peak memory 253260 kb
Host smart-34f8f69d-7845-4add-8aba-d8614ceaeb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605104049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.605104049
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3630759008
Short name T600
Test name
Test status
Simulation time 39871645353 ps
CPU time 79.09 seconds
Started Apr 15 01:24:41 PM PDT 24
Finished Apr 15 01:26:01 PM PDT 24
Peak memory 231428 kb
Host smart-e121b3a5-43de-472e-be42-a943283a10e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630759008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3630759008
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3676186252
Short name T684
Test name
Test status
Simulation time 18151222 ps
CPU time 1.06 seconds
Started Apr 15 01:24:33 PM PDT 24
Finished Apr 15 01:24:34 PM PDT 24
Peak memory 218152 kb
Host smart-2f5adadf-e69c-4852-8cab-2ac8b178f82d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676186252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3676186252
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3565645878
Short name T425
Test name
Test status
Simulation time 19889964431 ps
CPU time 13.75 seconds
Started Apr 15 01:24:41 PM PDT 24
Finished Apr 15 01:24:55 PM PDT 24
Peak memory 219420 kb
Host smart-9cfe28a0-a579-4eb3-bf67-ab37ac768e35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3565645878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3565645878
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2389280943
Short name T374
Test name
Test status
Simulation time 19566770726 ps
CPU time 30.17 seconds
Started Apr 15 01:24:37 PM PDT 24
Finished Apr 15 01:25:08 PM PDT 24
Peak memory 216604 kb
Host smart-15899b29-40b5-49be-8347-5ecf52fa48d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389280943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2389280943
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3891800563
Short name T534
Test name
Test status
Simulation time 13601536943 ps
CPU time 20.36 seconds
Started Apr 15 01:24:33 PM PDT 24
Finished Apr 15 01:24:54 PM PDT 24
Peak memory 216620 kb
Host smart-591de017-4dbb-443d-96d6-4b48adff4668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891800563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3891800563
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1325443012
Short name T634
Test name
Test status
Simulation time 232879696 ps
CPU time 1.18 seconds
Started Apr 15 01:24:37 PM PDT 24
Finished Apr 15 01:24:38 PM PDT 24
Peak memory 208300 kb
Host smart-a5160605-f21b-4628-a0a7-156d83627673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325443012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1325443012
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1821772930
Short name T527
Test name
Test status
Simulation time 41772710 ps
CPU time 0.8 seconds
Started Apr 15 01:24:36 PM PDT 24
Finished Apr 15 01:24:37 PM PDT 24
Peak memory 205824 kb
Host smart-a60aa04f-78ed-4759-9e66-5f7e0bb47f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821772930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1821772930
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3125942867
Short name T233
Test name
Test status
Simulation time 2228489489 ps
CPU time 8.13 seconds
Started Apr 15 01:24:38 PM PDT 24
Finished Apr 15 01:24:47 PM PDT 24
Peak memory 222920 kb
Host smart-71303208-63ae-4a4e-948e-e48e21776123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125942867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3125942867
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1055479275
Short name T542
Test name
Test status
Simulation time 13493129 ps
CPU time 0.67 seconds
Started Apr 15 01:24:49 PM PDT 24
Finished Apr 15 01:24:50 PM PDT 24
Peak memory 205396 kb
Host smart-950397ba-becf-4b58-bdf1-e5278825d4e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055479275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1055479275
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.450281780
Short name T21
Test name
Test status
Simulation time 220374222 ps
CPU time 0.77 seconds
Started Apr 15 01:24:44 PM PDT 24
Finished Apr 15 01:24:45 PM PDT 24
Peak memory 206648 kb
Host smart-7e06f481-834e-425c-8b69-73b88c8445d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450281780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.450281780
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.505922853
Short name T286
Test name
Test status
Simulation time 3270238577 ps
CPU time 59.69 seconds
Started Apr 15 01:24:47 PM PDT 24
Finished Apr 15 01:25:47 PM PDT 24
Peak memory 239412 kb
Host smart-7b0e88f4-2b75-4ec4-b996-6aee4ca691f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505922853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.505922853
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2336732740
Short name T574
Test name
Test status
Simulation time 56876405 ps
CPU time 1 seconds
Started Apr 15 01:24:42 PM PDT 24
Finished Apr 15 01:24:43 PM PDT 24
Peak memory 218216 kb
Host smart-73a2a156-facc-4276-8cc3-9096461dc005
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336732740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2336732740
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.4042149378
Short name T318
Test name
Test status
Simulation time 9667234753 ps
CPU time 12.2 seconds
Started Apr 15 01:24:41 PM PDT 24
Finished Apr 15 01:24:54 PM PDT 24
Peak memory 224784 kb
Host smart-c9f0bd20-dcb9-41d8-8ae0-f16482ecec74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042149378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.4042149378
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.349664090
Short name T627
Test name
Test status
Simulation time 318887478 ps
CPU time 5.52 seconds
Started Apr 15 01:24:46 PM PDT 24
Finished Apr 15 01:24:51 PM PDT 24
Peak memory 218916 kb
Host smart-c3a70594-cc5e-4edf-9006-979d854acc50
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=349664090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.349664090
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1346987892
Short name T648
Test name
Test status
Simulation time 38135631 ps
CPU time 0.89 seconds
Started Apr 15 01:24:47 PM PDT 24
Finished Apr 15 01:24:48 PM PDT 24
Peak memory 206644 kb
Host smart-9526bc08-4540-414b-bd17-dd19df21ac0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346987892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1346987892
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1979260166
Short name T544
Test name
Test status
Simulation time 77277618624 ps
CPU time 43.86 seconds
Started Apr 15 01:24:42 PM PDT 24
Finished Apr 15 01:25:26 PM PDT 24
Peak memory 216616 kb
Host smart-d8b26c1f-3ce7-45f4-8983-75e7f35da1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979260166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1979260166
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.276088506
Short name T489
Test name
Test status
Simulation time 51873668074 ps
CPU time 36.37 seconds
Started Apr 15 01:24:42 PM PDT 24
Finished Apr 15 01:25:19 PM PDT 24
Peak memory 216436 kb
Host smart-87850d90-8b32-411a-90b6-e16c71673d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276088506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.276088506
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2221616766
Short name T483
Test name
Test status
Simulation time 948059791 ps
CPU time 1.4 seconds
Started Apr 15 01:24:44 PM PDT 24
Finished Apr 15 01:24:45 PM PDT 24
Peak memory 216536 kb
Host smart-998c3d52-a6e4-459a-af30-1ac2177e680f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221616766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2221616766
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1858904799
Short name T721
Test name
Test status
Simulation time 76940788 ps
CPU time 0.94 seconds
Started Apr 15 01:24:42 PM PDT 24
Finished Apr 15 01:24:44 PM PDT 24
Peak memory 206904 kb
Host smart-9dea9704-b114-4d21-acc3-82f44d5eebbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858904799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1858904799
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3814652918
Short name T539
Test name
Test status
Simulation time 50627229 ps
CPU time 0.75 seconds
Started Apr 15 01:24:57 PM PDT 24
Finished Apr 15 01:24:58 PM PDT 24
Peak memory 204848 kb
Host smart-84e683b4-5e0c-4923-a762-d8a1043011e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814652918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3814652918
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2596526257
Short name T588
Test name
Test status
Simulation time 56022585 ps
CPU time 0.74 seconds
Started Apr 15 01:24:49 PM PDT 24
Finished Apr 15 01:24:50 PM PDT 24
Peak memory 205952 kb
Host smart-3724e29b-5871-496b-a86c-31322ff3d090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596526257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2596526257
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2676886383
Short name T647
Test name
Test status
Simulation time 30887980 ps
CPU time 1.01 seconds
Started Apr 15 01:24:46 PM PDT 24
Finished Apr 15 01:24:47 PM PDT 24
Peak memory 218212 kb
Host smart-c6c0860a-258b-4df2-96ad-f4db995e1b72
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676886383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2676886383
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3865251584
Short name T230
Test name
Test status
Simulation time 2258512966 ps
CPU time 10.23 seconds
Started Apr 15 01:24:51 PM PDT 24
Finished Apr 15 01:25:01 PM PDT 24
Peak memory 224952 kb
Host smart-f170a47e-dc33-4bd1-a6b2-a8540466da9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865251584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3865251584
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1668974071
Short name T470
Test name
Test status
Simulation time 970029711 ps
CPU time 7.08 seconds
Started Apr 15 01:24:53 PM PDT 24
Finished Apr 15 01:25:00 PM PDT 24
Peak memory 223104 kb
Host smart-c57f5cf2-e579-4897-b45f-f03692f3eb2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1668974071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1668974071
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3449800881
Short name T379
Test name
Test status
Simulation time 88621872044 ps
CPU time 51.78 seconds
Started Apr 15 01:24:46 PM PDT 24
Finished Apr 15 01:25:38 PM PDT 24
Peak memory 216544 kb
Host smart-45d462d1-1628-43ee-805a-020b46bb2c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449800881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3449800881
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.856822763
Short name T646
Test name
Test status
Simulation time 11926044036 ps
CPU time 7.5 seconds
Started Apr 15 01:24:47 PM PDT 24
Finished Apr 15 01:24:55 PM PDT 24
Peak memory 216580 kb
Host smart-c7cdfc96-337e-4d50-b89a-47339aeea666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856822763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.856822763
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1863935472
Short name T466
Test name
Test status
Simulation time 207388061 ps
CPU time 2.83 seconds
Started Apr 15 01:24:53 PM PDT 24
Finished Apr 15 01:24:56 PM PDT 24
Peak memory 216976 kb
Host smart-8de1f307-43e7-4897-b281-eef33ac165e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863935472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1863935472
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.184899978
Short name T533
Test name
Test status
Simulation time 44703046 ps
CPU time 0.72 seconds
Started Apr 15 01:24:47 PM PDT 24
Finished Apr 15 01:24:48 PM PDT 24
Peak memory 205868 kb
Host smart-69e17af0-b662-47fe-b635-e0ab59099c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184899978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.184899978
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2794929114
Short name T689
Test name
Test status
Simulation time 130821435 ps
CPU time 0.72 seconds
Started Apr 15 01:22:39 PM PDT 24
Finished Apr 15 01:22:40 PM PDT 24
Peak memory 204840 kb
Host smart-86fceccd-7cc0-4974-a78c-27f3284f96a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794929114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
794929114
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3827245686
Short name T555
Test name
Test status
Simulation time 22738132 ps
CPU time 0.79 seconds
Started Apr 15 01:22:35 PM PDT 24
Finished Apr 15 01:22:37 PM PDT 24
Peak memory 206624 kb
Host smart-3e767c08-affc-4af9-ac5f-a4d7e020bf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827245686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3827245686
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2655537542
Short name T599
Test name
Test status
Simulation time 6833225060 ps
CPU time 25.52 seconds
Started Apr 15 01:22:40 PM PDT 24
Finished Apr 15 01:23:06 PM PDT 24
Peak memory 235124 kb
Host smart-93c634b3-7e8c-43f0-bba6-a210b64fc674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655537542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2655537542
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.89070338
Short name T368
Test name
Test status
Simulation time 242506328 ps
CPU time 5.93 seconds
Started Apr 15 01:22:37 PM PDT 24
Finished Apr 15 01:22:43 PM PDT 24
Peak memory 223548 kb
Host smart-71e934fe-55f7-483a-90f7-9bb4fc47cd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89070338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.89070338
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1512310516
Short name T584
Test name
Test status
Simulation time 83606817 ps
CPU time 3.67 seconds
Started Apr 15 01:22:42 PM PDT 24
Finished Apr 15 01:22:47 PM PDT 24
Peak memory 232976 kb
Host smart-b7626792-965a-45d3-882f-61043392fd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512310516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1512310516
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2932972214
Short name T30
Test name
Test status
Simulation time 79391524 ps
CPU time 1.1 seconds
Started Apr 15 01:22:38 PM PDT 24
Finished Apr 15 01:22:39 PM PDT 24
Peak memory 216992 kb
Host smart-685c8441-6b84-4401-b717-08464d9481e1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932972214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2932972214
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3231250452
Short name T335
Test name
Test status
Simulation time 1235244349 ps
CPU time 5.05 seconds
Started Apr 15 01:22:35 PM PDT 24
Finished Apr 15 01:22:41 PM PDT 24
Peak memory 221768 kb
Host smart-fb6271d0-50b0-40a3-ad29-ee5962bf1a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231250452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3231250452
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1866204181
Short name T519
Test name
Test status
Simulation time 1567999357 ps
CPU time 17.76 seconds
Started Apr 15 01:22:41 PM PDT 24
Finished Apr 15 01:23:00 PM PDT 24
Peak memory 219300 kb
Host smart-a9f34786-f70c-4e0e-956e-dbbb5da9e254
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1866204181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1866204181
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1765036719
Short name T42
Test name
Test status
Simulation time 170860725 ps
CPU time 1.11 seconds
Started Apr 15 01:22:39 PM PDT 24
Finished Apr 15 01:22:41 PM PDT 24
Peak memory 235492 kb
Host smart-06f82674-8c4e-4054-9d0f-3f6edd13cdd5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765036719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1765036719
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1832239083
Short name T388
Test name
Test status
Simulation time 51904970099 ps
CPU time 26.68 seconds
Started Apr 15 01:22:36 PM PDT 24
Finished Apr 15 01:23:04 PM PDT 24
Peak memory 216620 kb
Host smart-b2c96153-4320-4444-8e6b-bfbeb3ad0885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832239083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1832239083
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.594147920
Short name T484
Test name
Test status
Simulation time 168527366 ps
CPU time 1.48 seconds
Started Apr 15 01:22:34 PM PDT 24
Finished Apr 15 01:22:36 PM PDT 24
Peak memory 207876 kb
Host smart-f888b717-2c87-4b8e-aa8b-808a7f5d115d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594147920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.594147920
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3805081018
Short name T598
Test name
Test status
Simulation time 114828081 ps
CPU time 1.33 seconds
Started Apr 15 01:22:35 PM PDT 24
Finished Apr 15 01:22:37 PM PDT 24
Peak memory 208624 kb
Host smart-464d595f-0384-4786-a74d-358c55bb41d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805081018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3805081018
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.279138623
Short name T450
Test name
Test status
Simulation time 185061622 ps
CPU time 1.03 seconds
Started Apr 15 01:22:38 PM PDT 24
Finished Apr 15 01:22:40 PM PDT 24
Peak memory 206888 kb
Host smart-46a9b838-41ba-4608-9edf-db6eb45306c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279138623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.279138623
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3346980846
Short name T682
Test name
Test status
Simulation time 14249256 ps
CPU time 0.72 seconds
Started Apr 15 01:25:06 PM PDT 24
Finished Apr 15 01:25:07 PM PDT 24
Peak memory 205352 kb
Host smart-ff117351-481f-4d9a-ad0f-857be16e8492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346980846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3346980846
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3754738795
Short name T422
Test name
Test status
Simulation time 37233652 ps
CPU time 0.78 seconds
Started Apr 15 01:24:56 PM PDT 24
Finished Apr 15 01:24:57 PM PDT 24
Peak memory 206664 kb
Host smart-7d1f6095-96ba-4fd1-aca6-007bdb464ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754738795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3754738795
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.20073102
Short name T651
Test name
Test status
Simulation time 4060188435 ps
CPU time 41.27 seconds
Started Apr 15 01:25:01 PM PDT 24
Finished Apr 15 01:25:43 PM PDT 24
Peak memory 233040 kb
Host smart-00815267-751e-4fbb-af04-828a375a47c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20073102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.20073102
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3256208543
Short name T216
Test name
Test status
Simulation time 977806630 ps
CPU time 6.69 seconds
Started Apr 15 01:24:58 PM PDT 24
Finished Apr 15 01:25:05 PM PDT 24
Peak memory 222400 kb
Host smart-7eb6205c-9326-4cc1-a1c2-b47676672932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256208543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3256208543
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3939776922
Short name T106
Test name
Test status
Simulation time 2431808279 ps
CPU time 11.91 seconds
Started Apr 15 01:25:02 PM PDT 24
Finished Apr 15 01:25:14 PM PDT 24
Peak memory 223016 kb
Host smart-af2a2185-a36d-4e45-9b2c-3f94c46bb0d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3939776922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3939776922
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1372397388
Short name T515
Test name
Test status
Simulation time 37930197 ps
CPU time 0.95 seconds
Started Apr 15 01:25:06 PM PDT 24
Finished Apr 15 01:25:07 PM PDT 24
Peak memory 207096 kb
Host smart-0494a950-ed0f-4245-bb6d-45c78d71cc3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372397388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1372397388
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.140392100
Short name T536
Test name
Test status
Simulation time 1491606025 ps
CPU time 21.27 seconds
Started Apr 15 01:25:01 PM PDT 24
Finished Apr 15 01:25:23 PM PDT 24
Peak memory 216820 kb
Host smart-fbf2769b-a6d9-4d9e-9d88-ea1e0f3280cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140392100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.140392100
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4024380714
Short name T540
Test name
Test status
Simulation time 45641890605 ps
CPU time 36.26 seconds
Started Apr 15 01:24:59 PM PDT 24
Finished Apr 15 01:25:35 PM PDT 24
Peak memory 216636 kb
Host smart-abba883f-fbb0-4245-9733-6e90709f3185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024380714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4024380714
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.630186271
Short name T734
Test name
Test status
Simulation time 102556920 ps
CPU time 1.28 seconds
Started Apr 15 01:24:58 PM PDT 24
Finished Apr 15 01:24:59 PM PDT 24
Peak memory 208488 kb
Host smart-ef8da7c4-0a30-4eb4-931c-1eac860ec2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630186271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.630186271
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1211899242
Short name T618
Test name
Test status
Simulation time 71761765 ps
CPU time 0.75 seconds
Started Apr 15 01:24:59 PM PDT 24
Finished Apr 15 01:25:00 PM PDT 24
Peak memory 205884 kb
Host smart-d03d34f1-f825-451a-a42d-55ae6f052d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211899242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1211899242
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.678778960
Short name T265
Test name
Test status
Simulation time 4055561024 ps
CPU time 5.15 seconds
Started Apr 15 01:24:59 PM PDT 24
Finished Apr 15 01:25:05 PM PDT 24
Peak memory 222868 kb
Host smart-07fc4f92-2417-4aca-a336-343d933f9959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678778960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.678778960
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3582534410
Short name T725
Test name
Test status
Simulation time 57305006 ps
CPU time 0.71 seconds
Started Apr 15 01:25:16 PM PDT 24
Finished Apr 15 01:25:17 PM PDT 24
Peak memory 204824 kb
Host smart-26440ec0-5d03-4649-96ba-0a82fcd59281
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582534410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3582534410
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3068440687
Short name T703
Test name
Test status
Simulation time 49767747 ps
CPU time 0.79 seconds
Started Apr 15 01:25:09 PM PDT 24
Finished Apr 15 01:25:10 PM PDT 24
Peak memory 206652 kb
Host smart-879e74a8-dd47-484d-8ab6-ed333e7f985e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068440687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3068440687
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3321150837
Short name T612
Test name
Test status
Simulation time 22300195435 ps
CPU time 143.92 seconds
Started Apr 15 01:25:13 PM PDT 24
Finished Apr 15 01:27:37 PM PDT 24
Peak memory 249448 kb
Host smart-e0589b27-b5c0-4529-a60d-9effb880d952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321150837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3321150837
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2501656657
Short name T39
Test name
Test status
Simulation time 1142881263 ps
CPU time 8.5 seconds
Started Apr 15 01:25:12 PM PDT 24
Finished Apr 15 01:25:21 PM PDT 24
Peak memory 224772 kb
Host smart-b3a870b2-435d-4738-87ad-16696adad727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501656657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2501656657
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2530774951
Short name T506
Test name
Test status
Simulation time 354455274 ps
CPU time 4.74 seconds
Started Apr 15 01:25:13 PM PDT 24
Finished Apr 15 01:25:18 PM PDT 24
Peak memory 218904 kb
Host smart-02059e77-24af-4820-86f8-6edca859a666
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2530774951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2530774951
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.4089794695
Short name T18
Test name
Test status
Simulation time 44938859 ps
CPU time 0.93 seconds
Started Apr 15 01:25:17 PM PDT 24
Finished Apr 15 01:25:19 PM PDT 24
Peak memory 206808 kb
Host smart-15e62011-ca9b-43b2-962d-d373842c3232
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089794695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.4089794695
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2113872179
Short name T120
Test name
Test status
Simulation time 25540377232 ps
CPU time 24.71 seconds
Started Apr 15 01:25:09 PM PDT 24
Finished Apr 15 01:25:34 PM PDT 24
Peak memory 216664 kb
Host smart-0d68cea7-763d-4f80-a566-24673437d2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113872179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2113872179
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2841771503
Short name T392
Test name
Test status
Simulation time 78151038 ps
CPU time 0.79 seconds
Started Apr 15 01:25:07 PM PDT 24
Finished Apr 15 01:25:09 PM PDT 24
Peak memory 205840 kb
Host smart-ba67c9bb-a0d0-423c-8544-3e148b020dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841771503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2841771503
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.4150872207
Short name T47
Test name
Test status
Simulation time 84413554 ps
CPU time 0.79 seconds
Started Apr 15 01:25:10 PM PDT 24
Finished Apr 15 01:25:12 PM PDT 24
Peak memory 205876 kb
Host smart-75c067d6-6635-4e3e-9582-e521f4027886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150872207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4150872207
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.53430243
Short name T693
Test name
Test status
Simulation time 25275858 ps
CPU time 0.73 seconds
Started Apr 15 01:25:16 PM PDT 24
Finished Apr 15 01:25:17 PM PDT 24
Peak memory 205896 kb
Host smart-ea6cabaf-b9a4-48d3-8819-6c9c8d63bd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53430243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.53430243
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1533455813
Short name T274
Test name
Test status
Simulation time 1196036558 ps
CPU time 4.49 seconds
Started Apr 15 01:25:22 PM PDT 24
Finished Apr 15 01:25:27 PM PDT 24
Peak memory 218900 kb
Host smart-402101c7-2f7c-4604-a87c-79d2bdb4cd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533455813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1533455813
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3114683613
Short name T659
Test name
Test status
Simulation time 2805400662 ps
CPU time 12.36 seconds
Started Apr 15 01:25:25 PM PDT 24
Finished Apr 15 01:25:38 PM PDT 24
Peak memory 220712 kb
Host smart-ff054301-02e0-46f5-bead-20cdeaf624ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3114683613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3114683613
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2140690745
Short name T58
Test name
Test status
Simulation time 4555188248 ps
CPU time 7.05 seconds
Started Apr 15 01:25:16 PM PDT 24
Finished Apr 15 01:25:23 PM PDT 24
Peak memory 216540 kb
Host smart-9a52e1ce-e37e-41e3-b512-51ac5a0631a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140690745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2140690745
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3340173899
Short name T407
Test name
Test status
Simulation time 3516656131 ps
CPU time 5.48 seconds
Started Apr 15 01:25:17 PM PDT 24
Finished Apr 15 01:25:23 PM PDT 24
Peak memory 216648 kb
Host smart-bcdac39b-4669-457c-9a30-c16faac1577a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340173899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3340173899
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1792813164
Short name T624
Test name
Test status
Simulation time 374369961 ps
CPU time 1.44 seconds
Started Apr 15 01:25:21 PM PDT 24
Finished Apr 15 01:25:23 PM PDT 24
Peak memory 216604 kb
Host smart-3e6e017e-5c29-47b2-873a-7f87752c4ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792813164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1792813164
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2877810773
Short name T549
Test name
Test status
Simulation time 520330683 ps
CPU time 1.15 seconds
Started Apr 15 01:25:30 PM PDT 24
Finished Apr 15 01:25:32 PM PDT 24
Peak memory 206848 kb
Host smart-ae351f25-5c6c-4dcd-9114-03511f8b93db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877810773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2877810773
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1757529897
Short name T273
Test name
Test status
Simulation time 185430902 ps
CPU time 4.47 seconds
Started Apr 15 01:25:20 PM PDT 24
Finished Apr 15 01:25:25 PM PDT 24
Peak memory 222964 kb
Host smart-a19fafad-50c7-462d-b3ef-1e92b3bad3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757529897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1757529897
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.532550801
Short name T662
Test name
Test status
Simulation time 15954347 ps
CPU time 0.76 seconds
Started Apr 15 01:25:32 PM PDT 24
Finished Apr 15 01:25:33 PM PDT 24
Peak memory 205404 kb
Host smart-ea928824-f5af-4568-8cd3-ba249d7927f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532550801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.532550801
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.554424167
Short name T617
Test name
Test status
Simulation time 10221178280 ps
CPU time 21.81 seconds
Started Apr 15 01:25:32 PM PDT 24
Finished Apr 15 01:25:54 PM PDT 24
Peak memory 219008 kb
Host smart-8b04fad0-2ba1-4502-b264-b574375b68d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554424167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.554424167
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2417087885
Short name T589
Test name
Test status
Simulation time 82763984 ps
CPU time 0.76 seconds
Started Apr 15 01:25:31 PM PDT 24
Finished Apr 15 01:25:32 PM PDT 24
Peak memory 206636 kb
Host smart-d121d9e2-73a6-4a42-911e-79f0bd30c875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417087885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2417087885
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1654844061
Short name T289
Test name
Test status
Simulation time 3788818150 ps
CPU time 17.57 seconds
Started Apr 15 01:25:30 PM PDT 24
Finished Apr 15 01:25:48 PM PDT 24
Peak memory 241180 kb
Host smart-d2b1f292-90f8-4099-9af9-4a9aae3af470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654844061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1654844061
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2565066422
Short name T733
Test name
Test status
Simulation time 2547118789 ps
CPU time 4.69 seconds
Started Apr 15 01:25:26 PM PDT 24
Finished Apr 15 01:25:31 PM PDT 24
Peak memory 234060 kb
Host smart-56139444-0b62-4a95-bd70-db8585c72161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565066422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2565066422
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3299856608
Short name T522
Test name
Test status
Simulation time 1130629331 ps
CPU time 10.14 seconds
Started Apr 15 01:25:31 PM PDT 24
Finished Apr 15 01:25:41 PM PDT 24
Peak memory 223056 kb
Host smart-f48ba791-e951-459e-b9b0-3474c8e6ee0e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3299856608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3299856608
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3297461467
Short name T389
Test name
Test status
Simulation time 4584658469 ps
CPU time 29.7 seconds
Started Apr 15 01:25:27 PM PDT 24
Finished Apr 15 01:25:57 PM PDT 24
Peak memory 218720 kb
Host smart-4a4f34e8-493b-4b2a-a635-2179e7b8237f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297461467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3297461467
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.4046981105
Short name T641
Test name
Test status
Simulation time 26178050619 ps
CPU time 18.41 seconds
Started Apr 15 01:25:28 PM PDT 24
Finished Apr 15 01:25:47 PM PDT 24
Peak memory 216560 kb
Host smart-819be21e-c2a2-4a16-9da6-e24983a932e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046981105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4046981105
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3720476293
Short name T55
Test name
Test status
Simulation time 94693441 ps
CPU time 0.83 seconds
Started Apr 15 01:25:28 PM PDT 24
Finished Apr 15 01:25:29 PM PDT 24
Peak memory 206568 kb
Host smart-4deaad5a-13cc-4457-b3e4-2449e4df7e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720476293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3720476293
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2777370912
Short name T447
Test name
Test status
Simulation time 176470069 ps
CPU time 0.87 seconds
Started Apr 15 01:25:28 PM PDT 24
Finished Apr 15 01:25:29 PM PDT 24
Peak memory 206884 kb
Host smart-c1a8fddc-fc22-4369-bd1b-5d0d902d107e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777370912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2777370912
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2253810388
Short name T36
Test name
Test status
Simulation time 2935526328 ps
CPU time 9.05 seconds
Started Apr 15 01:25:31 PM PDT 24
Finished Apr 15 01:25:41 PM PDT 24
Peak memory 223204 kb
Host smart-88c42842-8c09-420c-803e-292f9589fd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253810388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2253810388
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3517563471
Short name T462
Test name
Test status
Simulation time 50454151 ps
CPU time 0.71 seconds
Started Apr 15 01:25:39 PM PDT 24
Finished Apr 15 01:25:40 PM PDT 24
Peak memory 205672 kb
Host smart-60ac06f8-8ba2-42dc-8c7f-d6d6cd5a85cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517563471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3517563471
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1316642778
Short name T671
Test name
Test status
Simulation time 245951152 ps
CPU time 0.74 seconds
Started Apr 15 01:25:31 PM PDT 24
Finished Apr 15 01:25:32 PM PDT 24
Peak memory 206664 kb
Host smart-1d1cb2e4-f60e-44e1-87b1-89a3fa6c12c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316642778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1316642778
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3966945793
Short name T583
Test name
Test status
Simulation time 4352506094 ps
CPU time 64.98 seconds
Started Apr 15 01:25:38 PM PDT 24
Finished Apr 15 01:26:44 PM PDT 24
Peak memory 237784 kb
Host smart-60f0058f-6faa-4665-bd60-7783c954e0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966945793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3966945793
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1311447114
Short name T327
Test name
Test status
Simulation time 803328683 ps
CPU time 3.62 seconds
Started Apr 15 01:25:36 PM PDT 24
Finished Apr 15 01:25:40 PM PDT 24
Peak memory 223248 kb
Host smart-de16ccfc-6891-492a-95f4-ee79c47199ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311447114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1311447114
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.4274560205
Short name T424
Test name
Test status
Simulation time 58562623 ps
CPU time 2.32 seconds
Started Apr 15 01:25:40 PM PDT 24
Finished Apr 15 01:25:43 PM PDT 24
Peak memory 222564 kb
Host smart-2bfd0561-5f53-4d8b-8dfd-a6bf850ff105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274560205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.4274560205
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.105298638
Short name T572
Test name
Test status
Simulation time 585392316 ps
CPU time 6.57 seconds
Started Apr 15 01:25:38 PM PDT 24
Finished Apr 15 01:25:45 PM PDT 24
Peak memory 218988 kb
Host smart-a408c57b-cd48-45aa-b583-8785e9917b0e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=105298638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.105298638
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3381108487
Short name T616
Test name
Test status
Simulation time 7018744298 ps
CPU time 30.12 seconds
Started Apr 15 01:25:31 PM PDT 24
Finished Apr 15 01:26:02 PM PDT 24
Peak memory 216680 kb
Host smart-8df253f8-c327-4868-8e50-13cc62f34b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381108487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3381108487
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2661565695
Short name T419
Test name
Test status
Simulation time 378847523 ps
CPU time 1.34 seconds
Started Apr 15 01:25:31 PM PDT 24
Finished Apr 15 01:25:33 PM PDT 24
Peak memory 208140 kb
Host smart-a2d494c4-8c2d-42a2-90cd-0b8c59e6eb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661565695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2661565695
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.933603057
Short name T394
Test name
Test status
Simulation time 34628083 ps
CPU time 1.15 seconds
Started Apr 15 01:25:35 PM PDT 24
Finished Apr 15 01:25:37 PM PDT 24
Peak memory 208532 kb
Host smart-640290fe-7b14-4612-bd90-9c9de75be0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933603057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.933603057
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2868501886
Short name T622
Test name
Test status
Simulation time 63103729 ps
CPU time 0.94 seconds
Started Apr 15 01:25:30 PM PDT 24
Finished Apr 15 01:25:32 PM PDT 24
Peak memory 206884 kb
Host smart-06cd6c03-3478-4609-8d15-a0e5ba1961f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868501886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2868501886
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2501899590
Short name T281
Test name
Test status
Simulation time 22560364071 ps
CPU time 30.06 seconds
Started Apr 15 01:25:40 PM PDT 24
Finished Apr 15 01:26:11 PM PDT 24
Peak memory 224480 kb
Host smart-437a2cc0-bc43-40b2-b73d-122c37fea0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501899590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2501899590
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1412030810
Short name T718
Test name
Test status
Simulation time 23897204 ps
CPU time 0.72 seconds
Started Apr 15 01:25:54 PM PDT 24
Finished Apr 15 01:25:55 PM PDT 24
Peak memory 205740 kb
Host smart-7f8622e0-1b0e-4575-bd65-0bd24d9f8f9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412030810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1412030810
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1050454773
Short name T644
Test name
Test status
Simulation time 809012717 ps
CPU time 7.91 seconds
Started Apr 15 01:25:49 PM PDT 24
Finished Apr 15 01:25:58 PM PDT 24
Peak memory 224104 kb
Host smart-dcb3ce18-7662-44e3-8d5b-a7ab4ef7844e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050454773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1050454773
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1344070841
Short name T414
Test name
Test status
Simulation time 15848102 ps
CPU time 0.76 seconds
Started Apr 15 01:25:39 PM PDT 24
Finished Apr 15 01:25:40 PM PDT 24
Peak memory 206664 kb
Host smart-1cf4272f-712d-4103-85de-8cff7a276cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344070841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1344070841
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3081875583
Short name T284
Test name
Test status
Simulation time 1688080814 ps
CPU time 31.9 seconds
Started Apr 15 01:25:48 PM PDT 24
Finished Apr 15 01:26:20 PM PDT 24
Peak memory 249952 kb
Host smart-a6ff3d97-dcda-40b4-a527-b076ff07f0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081875583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3081875583
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2348007296
Short name T180
Test name
Test status
Simulation time 6387884345 ps
CPU time 59.9 seconds
Started Apr 15 01:25:50 PM PDT 24
Finished Apr 15 01:26:50 PM PDT 24
Peak memory 234432 kb
Host smart-24360dae-9001-4366-b829-2afcd4aea8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348007296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2348007296
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3130710650
Short name T261
Test name
Test status
Simulation time 796254130 ps
CPU time 10.36 seconds
Started Apr 15 01:25:45 PM PDT 24
Finished Apr 15 01:25:56 PM PDT 24
Peak memory 238288 kb
Host smart-b885a1d2-a342-4129-b526-0c4893ed05c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130710650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3130710650
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.433344355
Short name T722
Test name
Test status
Simulation time 336500421 ps
CPU time 4.82 seconds
Started Apr 15 01:25:48 PM PDT 24
Finished Apr 15 01:25:53 PM PDT 24
Peak memory 223036 kb
Host smart-f0d997c6-e0b5-4334-b48f-75d2e636a001
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=433344355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.433344355
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.246999807
Short name T104
Test name
Test status
Simulation time 3610990230 ps
CPU time 33.77 seconds
Started Apr 15 01:25:41 PM PDT 24
Finished Apr 15 01:26:16 PM PDT 24
Peak memory 216660 kb
Host smart-30965c80-8c69-4a53-8574-51c5b78501e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246999807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.246999807
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.754810954
Short name T438
Test name
Test status
Simulation time 6643994645 ps
CPU time 19.53 seconds
Started Apr 15 01:25:41 PM PDT 24
Finished Apr 15 01:26:01 PM PDT 24
Peak memory 216576 kb
Host smart-2248786b-ceda-480a-901f-d9e38548460a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754810954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.754810954
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.113519922
Short name T639
Test name
Test status
Simulation time 1714202307 ps
CPU time 4.22 seconds
Started Apr 15 01:25:46 PM PDT 24
Finished Apr 15 01:25:51 PM PDT 24
Peak memory 216740 kb
Host smart-504e364e-e920-46d8-8fc5-5a8bd087ea5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113519922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.113519922
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1748811672
Short name T15
Test name
Test status
Simulation time 63572456 ps
CPU time 0.8 seconds
Started Apr 15 01:25:44 PM PDT 24
Finished Apr 15 01:25:45 PM PDT 24
Peak memory 205852 kb
Host smart-9ddb4ff5-70ee-43d5-b95d-828303bdf54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748811672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1748811672
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2284815475
Short name T514
Test name
Test status
Simulation time 19179309 ps
CPU time 0.7 seconds
Started Apr 15 01:26:05 PM PDT 24
Finished Apr 15 01:26:06 PM PDT 24
Peak memory 205384 kb
Host smart-a9e7229d-3413-4300-8cd1-db00d9fcfed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284815475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2284815475
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2932449282
Short name T520
Test name
Test status
Simulation time 20678779 ps
CPU time 0.74 seconds
Started Apr 15 01:25:52 PM PDT 24
Finished Apr 15 01:25:53 PM PDT 24
Peak memory 206976 kb
Host smart-536c7a26-31be-4c9e-8cb8-eacfd6953d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932449282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2932449282
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1029629636
Short name T661
Test name
Test status
Simulation time 21655550012 ps
CPU time 137.64 seconds
Started Apr 15 01:25:58 PM PDT 24
Finished Apr 15 01:28:16 PM PDT 24
Peak memory 249424 kb
Host smart-737037db-46d1-4378-acaa-27e389904bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029629636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1029629636
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.811313113
Short name T248
Test name
Test status
Simulation time 15082851600 ps
CPU time 19.05 seconds
Started Apr 15 01:26:02 PM PDT 24
Finished Apr 15 01:26:21 PM PDT 24
Peak memory 223312 kb
Host smart-040ba88a-ea5e-4169-8609-f759f50669c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811313113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.811313113
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3703418619
Short name T251
Test name
Test status
Simulation time 323930495 ps
CPU time 2.86 seconds
Started Apr 15 01:25:59 PM PDT 24
Finished Apr 15 01:26:02 PM PDT 24
Peak memory 222932 kb
Host smart-31d836a6-bbe2-4c96-9f1a-00509a82e378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703418619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3703418619
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1581723721
Short name T678
Test name
Test status
Simulation time 3478746081 ps
CPU time 9.29 seconds
Started Apr 15 01:26:01 PM PDT 24
Finished Apr 15 01:26:11 PM PDT 24
Peak memory 222996 kb
Host smart-577a084c-3afb-420f-8e77-65c35d603d07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1581723721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1581723721
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2805259659
Short name T621
Test name
Test status
Simulation time 2637630329 ps
CPU time 8.94 seconds
Started Apr 15 01:25:53 PM PDT 24
Finished Apr 15 01:26:03 PM PDT 24
Peak memory 216616 kb
Host smart-ed508039-37c2-4469-97be-5714b6a2876c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805259659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2805259659
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1293207950
Short name T730
Test name
Test status
Simulation time 500449071 ps
CPU time 5.45 seconds
Started Apr 15 01:26:02 PM PDT 24
Finished Apr 15 01:26:08 PM PDT 24
Peak memory 216688 kb
Host smart-cc1924c0-024a-4e91-8de4-cec144050c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293207950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1293207950
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.4242034726
Short name T688
Test name
Test status
Simulation time 70217042 ps
CPU time 0.84 seconds
Started Apr 15 01:25:58 PM PDT 24
Finished Apr 15 01:25:59 PM PDT 24
Peak memory 206928 kb
Host smart-35fbbc85-5599-407e-b3ff-e78dd251654c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242034726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4242034726
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.131211528
Short name T192
Test name
Test status
Simulation time 13280934821 ps
CPU time 10.18 seconds
Started Apr 15 01:25:57 PM PDT 24
Finished Apr 15 01:26:08 PM PDT 24
Peak memory 218792 kb
Host smart-0614c781-c883-4cd0-a51b-f220c45bb721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131211528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.131211528
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.485662037
Short name T27
Test name
Test status
Simulation time 14510934 ps
CPU time 0.69 seconds
Started Apr 15 01:26:11 PM PDT 24
Finished Apr 15 01:26:12 PM PDT 24
Peak memory 205428 kb
Host smart-d6abbe24-130d-44f9-89fe-e0559ee25f72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485662037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.485662037
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2538734672
Short name T454
Test name
Test status
Simulation time 48113143 ps
CPU time 0.75 seconds
Started Apr 15 01:26:06 PM PDT 24
Finished Apr 15 01:26:07 PM PDT 24
Peak memory 205624 kb
Host smart-5255343d-5836-4276-af20-fc10d2bef140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538734672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2538734672
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3063320947
Short name T298
Test name
Test status
Simulation time 41354763764 ps
CPU time 93.76 seconds
Started Apr 15 01:26:11 PM PDT 24
Finished Apr 15 01:27:46 PM PDT 24
Peak memory 234044 kb
Host smart-d3c2beed-87c5-460f-95de-a628639b658a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063320947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3063320947
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4101407682
Short name T174
Test name
Test status
Simulation time 3295354524 ps
CPU time 12.22 seconds
Started Apr 15 01:26:08 PM PDT 24
Finished Apr 15 01:26:21 PM PDT 24
Peak memory 216984 kb
Host smart-96442bca-509f-4485-92f0-05cdfc8abfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101407682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4101407682
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.4285711001
Short name T220
Test name
Test status
Simulation time 4399979366 ps
CPU time 8.53 seconds
Started Apr 15 01:26:05 PM PDT 24
Finished Apr 15 01:26:14 PM PDT 24
Peak memory 221356 kb
Host smart-36fa2439-20bf-4c4a-b6d6-777fdbb9b5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285711001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4285711001
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3657203356
Short name T429
Test name
Test status
Simulation time 91838704 ps
CPU time 3.83 seconds
Started Apr 15 01:26:12 PM PDT 24
Finished Apr 15 01:26:16 PM PDT 24
Peak memory 223012 kb
Host smart-398143d8-8c20-45f4-aa9c-291831d4fbc8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3657203356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3657203356
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2819760303
Short name T409
Test name
Test status
Simulation time 7260909467 ps
CPU time 5.18 seconds
Started Apr 15 01:26:05 PM PDT 24
Finished Apr 15 01:26:10 PM PDT 24
Peak memory 216564 kb
Host smart-57bcd43a-9fd9-43b8-8f3c-414c9decee2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819760303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2819760303
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3311991614
Short name T393
Test name
Test status
Simulation time 27456796 ps
CPU time 0.8 seconds
Started Apr 15 01:26:04 PM PDT 24
Finished Apr 15 01:26:06 PM PDT 24
Peak memory 206880 kb
Host smart-82eb6a30-433f-4a03-9292-68794162e944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311991614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3311991614
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1608973297
Short name T708
Test name
Test status
Simulation time 14263560 ps
CPU time 0.7 seconds
Started Apr 15 01:26:05 PM PDT 24
Finished Apr 15 01:26:06 PM PDT 24
Peak memory 205892 kb
Host smart-93c7ff0c-0738-48ad-95f6-b69a243e1a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608973297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1608973297
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1924594965
Short name T449
Test name
Test status
Simulation time 15484109 ps
CPU time 0.71 seconds
Started Apr 15 01:26:18 PM PDT 24
Finished Apr 15 01:26:19 PM PDT 24
Peak memory 205368 kb
Host smart-68c1e9ad-e0c0-4876-a1d7-7e4527fce388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924594965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1924594965
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3697301254
Short name T524
Test name
Test status
Simulation time 21331109 ps
CPU time 0.82 seconds
Started Apr 15 01:26:09 PM PDT 24
Finished Apr 15 01:26:10 PM PDT 24
Peak memory 207152 kb
Host smart-6e6b2819-8cc2-42ef-9ba6-6416ea2b3ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697301254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3697301254
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.317919811
Short name T361
Test name
Test status
Simulation time 7462930927 ps
CPU time 99.12 seconds
Started Apr 15 01:26:16 PM PDT 24
Finished Apr 15 01:27:55 PM PDT 24
Peak memory 232772 kb
Host smart-d8172ab8-6629-4ca0-9260-ad7a240f96c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317919811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.317919811
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1997205878
Short name T270
Test name
Test status
Simulation time 1159531471 ps
CPU time 4.94 seconds
Started Apr 15 01:26:14 PM PDT 24
Finished Apr 15 01:26:19 PM PDT 24
Peak memory 219176 kb
Host smart-40160c55-a9e3-4a8f-baa3-e6712bd8db6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997205878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1997205878
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2513597482
Short name T731
Test name
Test status
Simulation time 4636143025 ps
CPU time 8.46 seconds
Started Apr 15 01:26:14 PM PDT 24
Finished Apr 15 01:26:23 PM PDT 24
Peak memory 223036 kb
Host smart-996f70e7-6a54-48ba-8a85-90ff7b88dc98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2513597482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2513597482
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1156706938
Short name T395
Test name
Test status
Simulation time 510815458 ps
CPU time 5.52 seconds
Started Apr 15 01:26:14 PM PDT 24
Finished Apr 15 01:26:20 PM PDT 24
Peak memory 216632 kb
Host smart-941fa222-b249-4b0b-926a-f851dd6ba4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156706938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1156706938
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2759623803
Short name T571
Test name
Test status
Simulation time 1503354750 ps
CPU time 8.61 seconds
Started Apr 15 01:26:13 PM PDT 24
Finished Apr 15 01:26:22 PM PDT 24
Peak memory 216520 kb
Host smart-9c1d370f-fe34-4d56-b089-5ddda0acd0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759623803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2759623803
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3359646056
Short name T653
Test name
Test status
Simulation time 65315136 ps
CPU time 1.05 seconds
Started Apr 15 01:26:14 PM PDT 24
Finished Apr 15 01:26:15 PM PDT 24
Peak memory 208088 kb
Host smart-a23d4832-d701-40da-aa68-d4bfa1dc1d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359646056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3359646056
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.759393953
Short name T453
Test name
Test status
Simulation time 113126566 ps
CPU time 0.9 seconds
Started Apr 15 01:26:13 PM PDT 24
Finished Apr 15 01:26:15 PM PDT 24
Peak memory 205744 kb
Host smart-1614145f-a9f2-4b36-8781-0fd93a4860a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759393953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.759393953
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3031303828
Short name T309
Test name
Test status
Simulation time 13032299523 ps
CPU time 19.28 seconds
Started Apr 15 01:26:14 PM PDT 24
Finished Apr 15 01:26:33 PM PDT 24
Peak memory 232968 kb
Host smart-0f1099ab-ee09-4a39-a1b0-abeec11cec47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031303828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3031303828
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3636239841
Short name T413
Test name
Test status
Simulation time 80330281 ps
CPU time 0.71 seconds
Started Apr 15 01:26:36 PM PDT 24
Finished Apr 15 01:26:37 PM PDT 24
Peak memory 205392 kb
Host smart-a4a8d851-ea04-41fd-810e-c6213569c1b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636239841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3636239841
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1072293703
Short name T90
Test name
Test status
Simulation time 1145493201 ps
CPU time 5.03 seconds
Started Apr 15 01:26:30 PM PDT 24
Finished Apr 15 01:26:36 PM PDT 24
Peak memory 223000 kb
Host smart-2cc311d8-f669-45a8-88e9-d68695812098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072293703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1072293703
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.142132181
Short name T715
Test name
Test status
Simulation time 21524196 ps
CPU time 0.75 seconds
Started Apr 15 01:26:20 PM PDT 24
Finished Apr 15 01:26:21 PM PDT 24
Peak memory 206916 kb
Host smart-de58bc68-74c0-4218-87a0-63f3ca9b254a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142132181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.142132181
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3400646887
Short name T198
Test name
Test status
Simulation time 24454639585 ps
CPU time 22.41 seconds
Started Apr 15 01:26:28 PM PDT 24
Finished Apr 15 01:26:51 PM PDT 24
Peak memory 223984 kb
Host smart-56af86a4-3c2c-47cb-897a-fa6c79f78ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400646887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3400646887
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.273876989
Short name T277
Test name
Test status
Simulation time 8559782689 ps
CPU time 15.75 seconds
Started Apr 15 01:26:30 PM PDT 24
Finished Apr 15 01:26:46 PM PDT 24
Peak memory 235980 kb
Host smart-e7a67c40-69f7-41b3-91d9-091966c5567c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273876989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.273876989
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2915516960
Short name T200
Test name
Test status
Simulation time 287505782 ps
CPU time 3.13 seconds
Started Apr 15 01:26:26 PM PDT 24
Finished Apr 15 01:26:29 PM PDT 24
Peak memory 223268 kb
Host smart-bec63b6b-1be4-4e6a-9060-a2051a925b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915516960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2915516960
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3243753293
Short name T723
Test name
Test status
Simulation time 6218828807 ps
CPU time 16.41 seconds
Started Apr 15 01:26:30 PM PDT 24
Finished Apr 15 01:26:47 PM PDT 24
Peak memory 219516 kb
Host smart-9e47d9bd-a109-4787-836b-1c487d197b80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3243753293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3243753293
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.679974873
Short name T434
Test name
Test status
Simulation time 48306388 ps
CPU time 0.98 seconds
Started Apr 15 01:26:37 PM PDT 24
Finished Apr 15 01:26:39 PM PDT 24
Peak memory 206948 kb
Host smart-e1db38e4-8ad5-4e8f-8692-98c74cb850b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679974873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.679974873
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.269458291
Short name T375
Test name
Test status
Simulation time 2008850339 ps
CPU time 15.31 seconds
Started Apr 15 01:26:29 PM PDT 24
Finished Apr 15 01:26:44 PM PDT 24
Peak memory 219996 kb
Host smart-3d0c129f-05a9-4820-9413-f1d4a9daaaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269458291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.269458291
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3698164549
Short name T567
Test name
Test status
Simulation time 419338764 ps
CPU time 0.92 seconds
Started Apr 15 01:26:24 PM PDT 24
Finished Apr 15 01:26:25 PM PDT 24
Peak memory 205884 kb
Host smart-2b96763f-b0c3-4323-83f4-70bd345852f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698164549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3698164549
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2885336169
Short name T61
Test name
Test status
Simulation time 56851868 ps
CPU time 1.56 seconds
Started Apr 15 01:26:28 PM PDT 24
Finished Apr 15 01:26:30 PM PDT 24
Peak memory 216564 kb
Host smart-18d386c5-d532-4d5b-ad61-6d6495c4fd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885336169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2885336169
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.637386407
Short name T412
Test name
Test status
Simulation time 56570351 ps
CPU time 0.72 seconds
Started Apr 15 01:26:29 PM PDT 24
Finished Apr 15 01:26:30 PM PDT 24
Peak memory 205860 kb
Host smart-6c690f29-9519-4e2d-a4a1-00455e6d0b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637386407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.637386407
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.202268115
Short name T28
Test name
Test status
Simulation time 34633830 ps
CPU time 0.71 seconds
Started Apr 15 01:22:50 PM PDT 24
Finished Apr 15 01:22:51 PM PDT 24
Peak memory 205744 kb
Host smart-6eeb1150-d05a-47d8-a917-6aedf41fb907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202268115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.202268115
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3811070801
Short name T707
Test name
Test status
Simulation time 21889104 ps
CPU time 0.74 seconds
Started Apr 15 01:22:45 PM PDT 24
Finished Apr 15 01:22:46 PM PDT 24
Peak memory 206984 kb
Host smart-4fc15a93-c0fe-43fd-987a-1d1941354711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811070801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3811070801
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.4155617555
Short name T53
Test name
Test status
Simulation time 3671521882 ps
CPU time 33.42 seconds
Started Apr 15 01:22:43 PM PDT 24
Finished Apr 15 01:23:17 PM PDT 24
Peak memory 250056 kb
Host smart-2cbeffd5-2265-4931-b495-df0a188db1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155617555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.4155617555
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3276025359
Short name T177
Test name
Test status
Simulation time 526728123 ps
CPU time 8.37 seconds
Started Apr 15 01:22:45 PM PDT 24
Finished Apr 15 01:22:54 PM PDT 24
Peak memory 222320 kb
Host smart-5cb0c7f0-b1c4-492f-aa57-2eef8bb91f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276025359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3276025359
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1564213070
Short name T477
Test name
Test status
Simulation time 1917250683 ps
CPU time 9.27 seconds
Started Apr 15 01:22:45 PM PDT 24
Finished Apr 15 01:22:55 PM PDT 24
Peak memory 232940 kb
Host smart-4913bf76-0571-49d1-8995-844232de7c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564213070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1564213070
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2348649555
Short name T1
Test name
Test status
Simulation time 18185227 ps
CPU time 0.99 seconds
Started Apr 15 01:22:45 PM PDT 24
Finished Apr 15 01:22:46 PM PDT 24
Peak memory 218204 kb
Host smart-9bbf06c7-05c8-4d07-ad65-1d885cb5d93a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348649555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2348649555
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1876790857
Short name T532
Test name
Test status
Simulation time 1170477980 ps
CPU time 11.72 seconds
Started Apr 15 01:22:43 PM PDT 24
Finished Apr 15 01:22:56 PM PDT 24
Peak memory 221664 kb
Host smart-3d712960-3d34-4858-8d5d-74f703d14065
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1876790857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1876790857
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.643655562
Short name T41
Test name
Test status
Simulation time 218851665 ps
CPU time 1.05 seconds
Started Apr 15 01:22:52 PM PDT 24
Finished Apr 15 01:22:53 PM PDT 24
Peak memory 235412 kb
Host smart-789d8e93-81ee-4b31-b482-13bf2d89c0b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643655562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.643655562
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3566958941
Short name T665
Test name
Test status
Simulation time 2151534652 ps
CPU time 3.3 seconds
Started Apr 15 01:22:43 PM PDT 24
Finished Apr 15 01:22:47 PM PDT 24
Peak memory 216844 kb
Host smart-a815eedf-19e4-4639-b451-748b1e971a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566958941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3566958941
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3036206560
Short name T685
Test name
Test status
Simulation time 205485964 ps
CPU time 2.84 seconds
Started Apr 15 01:22:43 PM PDT 24
Finished Apr 15 01:22:46 PM PDT 24
Peak memory 216596 kb
Host smart-ad86d341-3595-43c7-912c-ae7d201a2574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036206560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3036206560
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.78730544
Short name T406
Test name
Test status
Simulation time 22294411 ps
CPU time 0.76 seconds
Started Apr 15 01:22:43 PM PDT 24
Finished Apr 15 01:22:44 PM PDT 24
Peak memory 205856 kb
Host smart-e4e863fe-98e6-4aa8-b078-13e03dd2a5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78730544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.78730544
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3598463330
Short name T481
Test name
Test status
Simulation time 14698707 ps
CPU time 0.71 seconds
Started Apr 15 01:26:43 PM PDT 24
Finished Apr 15 01:26:44 PM PDT 24
Peak memory 205392 kb
Host smart-83c5fe67-a1ee-4ad9-9cc3-0d499a453ecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598463330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3598463330
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3505203447
Short name T610
Test name
Test status
Simulation time 1065639658 ps
CPU time 13.28 seconds
Started Apr 15 01:26:39 PM PDT 24
Finished Apr 15 01:26:52 PM PDT 24
Peak memory 223092 kb
Host smart-ad9778b0-7207-48e4-a934-085c73eb67c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505203447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3505203447
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.4196430047
Short name T428
Test name
Test status
Simulation time 62375858 ps
CPU time 0.77 seconds
Started Apr 15 01:26:37 PM PDT 24
Finished Apr 15 01:26:39 PM PDT 24
Peak memory 206636 kb
Host smart-6db1d196-64e7-468a-bea8-9c147fd8f3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196430047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.4196430047
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3927012622
Short name T288
Test name
Test status
Simulation time 2794715088 ps
CPU time 20.24 seconds
Started Apr 15 01:26:38 PM PDT 24
Finished Apr 15 01:26:59 PM PDT 24
Peak memory 241176 kb
Host smart-17d3cedb-53ba-47d1-94a5-6eaff0b8107f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927012622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3927012622
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1243242531
Short name T480
Test name
Test status
Simulation time 504985168 ps
CPU time 4.17 seconds
Started Apr 15 01:26:39 PM PDT 24
Finished Apr 15 01:26:44 PM PDT 24
Peak memory 224748 kb
Host smart-b468521a-73a1-40df-8ccd-97de8df8ac8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243242531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1243242531
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.4176252053
Short name T328
Test name
Test status
Simulation time 231032560 ps
CPU time 3.41 seconds
Started Apr 15 01:26:40 PM PDT 24
Finished Apr 15 01:26:44 PM PDT 24
Peak memory 218880 kb
Host smart-238a2e4c-7582-4b5e-b4e0-afb5e9637909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176252053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4176252053
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.936835095
Short name T649
Test name
Test status
Simulation time 211445339 ps
CPU time 4.79 seconds
Started Apr 15 01:26:40 PM PDT 24
Finished Apr 15 01:26:46 PM PDT 24
Peak memory 222444 kb
Host smart-09cc2023-f25d-443e-b7e3-43a76764fdf8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=936835095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.936835095
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3193935184
Short name T560
Test name
Test status
Simulation time 1261881303 ps
CPU time 7.12 seconds
Started Apr 15 01:26:36 PM PDT 24
Finished Apr 15 01:26:43 PM PDT 24
Peak memory 216532 kb
Host smart-eb60cf53-dacf-428b-a8f2-72e0946249fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193935184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3193935184
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.478809160
Short name T735
Test name
Test status
Simulation time 6512360391 ps
CPU time 18.71 seconds
Started Apr 15 01:26:38 PM PDT 24
Finished Apr 15 01:26:57 PM PDT 24
Peak memory 216596 kb
Host smart-efd926ba-60be-452a-8978-6860c633ea00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478809160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.478809160
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3605760822
Short name T427
Test name
Test status
Simulation time 506056976 ps
CPU time 1.28 seconds
Started Apr 15 01:26:41 PM PDT 24
Finished Apr 15 01:26:42 PM PDT 24
Peak memory 208100 kb
Host smart-3db335b0-ec88-4b1c-8b3c-2a46ccae85d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605760822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3605760822
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2012741550
Short name T461
Test name
Test status
Simulation time 273267736 ps
CPU time 1.08 seconds
Started Apr 15 01:26:40 PM PDT 24
Finished Apr 15 01:26:41 PM PDT 24
Peak memory 206916 kb
Host smart-bbe286c9-1bf9-4e4a-8423-c057f8c689cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012741550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2012741550
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1199833099
Short name T479
Test name
Test status
Simulation time 13956637 ps
CPU time 0.69 seconds
Started Apr 15 01:26:51 PM PDT 24
Finished Apr 15 01:26:53 PM PDT 24
Peak memory 205416 kb
Host smart-4ab1b0b9-e863-4620-a233-8706cbc3f6c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199833099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1199833099
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2110800318
Short name T185
Test name
Test status
Simulation time 2784259560 ps
CPU time 3.99 seconds
Started Apr 15 01:26:51 PM PDT 24
Finished Apr 15 01:26:56 PM PDT 24
Peak memory 223224 kb
Host smart-e7845f33-edc6-458c-907a-6db2779aacc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110800318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2110800318
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.901030480
Short name T554
Test name
Test status
Simulation time 13446775 ps
CPU time 0.72 seconds
Started Apr 15 01:26:43 PM PDT 24
Finished Apr 15 01:26:44 PM PDT 24
Peak memory 206968 kb
Host smart-ece3b931-1a89-4d45-9b7e-dc5c9814d05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901030480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.901030480
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.929438026
Short name T371
Test name
Test status
Simulation time 2212924449 ps
CPU time 27.41 seconds
Started Apr 15 01:26:54 PM PDT 24
Finished Apr 15 01:27:22 PM PDT 24
Peak memory 249424 kb
Host smart-1a43c4d4-de49-4c98-91fb-c24a87e0b06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929438026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.929438026
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1092614870
Short name T193
Test name
Test status
Simulation time 376026250 ps
CPU time 2.87 seconds
Started Apr 15 01:26:48 PM PDT 24
Finished Apr 15 01:26:52 PM PDT 24
Peak memory 216948 kb
Host smart-745dfc57-cd36-4170-9d4a-77688a6d9c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092614870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1092614870
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1943364508
Short name T358
Test name
Test status
Simulation time 14554120764 ps
CPU time 22.65 seconds
Started Apr 15 01:26:52 PM PDT 24
Finished Apr 15 01:27:15 PM PDT 24
Peak memory 220672 kb
Host smart-85643b98-28b8-49a9-adb2-bbfb7a1eff88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943364508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1943364508
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2464579716
Short name T440
Test name
Test status
Simulation time 1272720093 ps
CPU time 6.27 seconds
Started Apr 15 01:26:53 PM PDT 24
Finished Apr 15 01:27:00 PM PDT 24
Peak memory 221300 kb
Host smart-7bc3e033-5867-4d51-b3e0-f4c798b90b39
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2464579716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2464579716
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1327019194
Short name T403
Test name
Test status
Simulation time 171302719 ps
CPU time 3.26 seconds
Started Apr 15 01:26:42 PM PDT 24
Finished Apr 15 01:26:46 PM PDT 24
Peak memory 216588 kb
Host smart-1118596b-7529-48d2-91e5-e062f6bbfd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327019194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1327019194
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1231300214
Short name T687
Test name
Test status
Simulation time 29092983363 ps
CPU time 16.69 seconds
Started Apr 15 01:26:42 PM PDT 24
Finished Apr 15 01:27:00 PM PDT 24
Peak memory 216604 kb
Host smart-a60d5e58-6f5e-4a79-81cc-09cab8b26ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231300214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1231300214
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.584046229
Short name T402
Test name
Test status
Simulation time 913732417 ps
CPU time 2.86 seconds
Started Apr 15 01:26:48 PM PDT 24
Finished Apr 15 01:26:51 PM PDT 24
Peak memory 216776 kb
Host smart-22598a91-2d70-47c1-b5dd-6319ba7915ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584046229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.584046229
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.4287163584
Short name T729
Test name
Test status
Simulation time 23201073 ps
CPU time 0.71 seconds
Started Apr 15 01:26:49 PM PDT 24
Finished Apr 15 01:26:50 PM PDT 24
Peak memory 205880 kb
Host smart-60071673-40c3-40df-90cd-c979ffac66a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287163584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.4287163584
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.25786183
Short name T700
Test name
Test status
Simulation time 14410433 ps
CPU time 0.71 seconds
Started Apr 15 01:27:15 PM PDT 24
Finished Apr 15 01:27:16 PM PDT 24
Peak memory 205380 kb
Host smart-fadb24e6-54ee-48cd-9801-9f04d6883652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25786183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.25786183
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.480677175
Short name T19
Test name
Test status
Simulation time 16508857 ps
CPU time 0.77 seconds
Started Apr 15 01:26:56 PM PDT 24
Finished Apr 15 01:26:57 PM PDT 24
Peak memory 206920 kb
Host smart-163b3bf9-8e02-4eb2-923b-d8670f178d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480677175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.480677175
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2557676406
Short name T366
Test name
Test status
Simulation time 1121621137 ps
CPU time 26.13 seconds
Started Apr 15 01:27:09 PM PDT 24
Finished Apr 15 01:27:35 PM PDT 24
Peak memory 250612 kb
Host smart-8ee0e354-6752-483b-8c6c-38ddbc367951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557676406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2557676406
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.4292134448
Short name T332
Test name
Test status
Simulation time 1999912542 ps
CPU time 12.06 seconds
Started Apr 15 01:27:00 PM PDT 24
Finished Apr 15 01:27:13 PM PDT 24
Peak memory 224148 kb
Host smart-3ccad88f-fcc4-47a3-877c-7d2c8cd0510e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292134448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.4292134448
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2439329966
Short name T168
Test name
Test status
Simulation time 109694943 ps
CPU time 2.24 seconds
Started Apr 15 01:26:59 PM PDT 24
Finished Apr 15 01:27:02 PM PDT 24
Peak memory 222692 kb
Host smart-63ecf4e6-24a9-4e7b-84ed-915eb73f0aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439329966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2439329966
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3235449069
Short name T190
Test name
Test status
Simulation time 1810249893 ps
CPU time 3.23 seconds
Started Apr 15 01:27:02 PM PDT 24
Finished Apr 15 01:27:05 PM PDT 24
Peak memory 218592 kb
Host smart-f12eee9f-2544-4486-b674-8d5d0ca598b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235449069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3235449069
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.366177019
Short name T585
Test name
Test status
Simulation time 418783883 ps
CPU time 5.88 seconds
Started Apr 15 01:27:11 PM PDT 24
Finished Apr 15 01:27:17 PM PDT 24
Peak memory 223004 kb
Host smart-a13865fc-b017-4b20-9e33-febb6e240aab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=366177019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.366177019
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1286586611
Short name T397
Test name
Test status
Simulation time 101292601549 ps
CPU time 38.45 seconds
Started Apr 15 01:26:57 PM PDT 24
Finished Apr 15 01:27:36 PM PDT 24
Peak memory 216584 kb
Host smart-b07603ed-119e-493a-a499-134575a34e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286586611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1286586611
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2380284328
Short name T736
Test name
Test status
Simulation time 3407098799 ps
CPU time 6.77 seconds
Started Apr 15 01:26:55 PM PDT 24
Finished Apr 15 01:27:02 PM PDT 24
Peak memory 216560 kb
Host smart-c2dce95b-1999-4505-bcea-3e04d3c26b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380284328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2380284328
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3769764975
Short name T404
Test name
Test status
Simulation time 368661537 ps
CPU time 1.43 seconds
Started Apr 15 01:27:01 PM PDT 24
Finished Apr 15 01:27:03 PM PDT 24
Peak memory 216660 kb
Host smart-0164587f-831b-4fab-b27e-7c37be9a8195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769764975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3769764975
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3020982126
Short name T739
Test name
Test status
Simulation time 373236801 ps
CPU time 0.97 seconds
Started Apr 15 01:26:55 PM PDT 24
Finished Apr 15 01:26:56 PM PDT 24
Peak memory 206884 kb
Host smart-44cb2a57-36d1-431d-aeed-0652781ae2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020982126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3020982126
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.4051415771
Short name T46
Test name
Test status
Simulation time 2605469565 ps
CPU time 4.76 seconds
Started Apr 15 01:27:04 PM PDT 24
Finished Apr 15 01:27:09 PM PDT 24
Peak memory 220292 kb
Host smart-3661c1d2-ec12-496b-8bfb-d9ca6f99db5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051415771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.4051415771
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3254420398
Short name T446
Test name
Test status
Simulation time 37208892 ps
CPU time 0.71 seconds
Started Apr 15 01:27:23 PM PDT 24
Finished Apr 15 01:27:24 PM PDT 24
Peak memory 205720 kb
Host smart-69a0cc85-21a8-455d-ba3c-45957a1b604a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254420398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3254420398
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3543992252
Short name T492
Test name
Test status
Simulation time 20730641 ps
CPU time 0.77 seconds
Started Apr 15 01:27:14 PM PDT 24
Finished Apr 15 01:27:15 PM PDT 24
Peak memory 206660 kb
Host smart-7fde81e3-82df-433f-88bb-059a4289ed26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543992252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3543992252
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.4151188283
Short name T369
Test name
Test status
Simulation time 227806845 ps
CPU time 9.85 seconds
Started Apr 15 01:27:19 PM PDT 24
Finished Apr 15 01:27:29 PM PDT 24
Peak memory 235144 kb
Host smart-b971528f-95f7-4abf-a206-9ca45d51c639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151188283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.4151188283
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1676979096
Short name T162
Test name
Test status
Simulation time 29913634182 ps
CPU time 72.94 seconds
Started Apr 15 01:27:18 PM PDT 24
Finished Apr 15 01:28:31 PM PDT 24
Peak memory 232720 kb
Host smart-e84d707d-bdd1-4b49-a9e8-342621e9945d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676979096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1676979096
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2881473907
Short name T204
Test name
Test status
Simulation time 618420531 ps
CPU time 4.12 seconds
Started Apr 15 01:27:17 PM PDT 24
Finished Apr 15 01:27:21 PM PDT 24
Peak memory 232400 kb
Host smart-a97383e8-da43-4c7b-81c6-b1694605f1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881473907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2881473907
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2775710877
Short name T326
Test name
Test status
Simulation time 1325114054 ps
CPU time 4.26 seconds
Started Apr 15 01:27:18 PM PDT 24
Finished Apr 15 01:27:22 PM PDT 24
Peak memory 223984 kb
Host smart-848d08d5-56ab-472e-beb7-e1e46540f488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775710877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2775710877
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2073161071
Short name T472
Test name
Test status
Simulation time 8503450517 ps
CPU time 18.64 seconds
Started Apr 15 01:27:17 PM PDT 24
Finished Apr 15 01:27:36 PM PDT 24
Peak memory 219132 kb
Host smart-1ed6bc67-fdd3-4cca-bb2c-4021719bc183
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2073161071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2073161071
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1404662450
Short name T590
Test name
Test status
Simulation time 1770520004 ps
CPU time 9.95 seconds
Started Apr 15 01:27:15 PM PDT 24
Finished Apr 15 01:27:26 PM PDT 24
Peak memory 216544 kb
Host smart-494f3de3-6eff-4584-bbf8-312329336e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404662450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1404662450
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.281152525
Short name T83
Test name
Test status
Simulation time 1047681260 ps
CPU time 2.14 seconds
Started Apr 15 01:27:15 PM PDT 24
Finished Apr 15 01:27:18 PM PDT 24
Peak memory 216128 kb
Host smart-88ce53e6-7ebd-4f10-b08b-1de7c73d818b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281152525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.281152525
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.422346919
Short name T576
Test name
Test status
Simulation time 172377168 ps
CPU time 1.94 seconds
Started Apr 15 01:27:16 PM PDT 24
Finished Apr 15 01:27:18 PM PDT 24
Peak memory 216528 kb
Host smart-3ab2a43e-4c4b-4bd8-9758-44d964188761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422346919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.422346919
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.697361221
Short name T562
Test name
Test status
Simulation time 19597940 ps
CPU time 0.75 seconds
Started Apr 15 01:27:15 PM PDT 24
Finished Apr 15 01:27:16 PM PDT 24
Peak memory 205888 kb
Host smart-d19c797c-3218-40b1-bff7-893515516cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697361221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.697361221
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2783622294
Short name T5
Test name
Test status
Simulation time 46290846917 ps
CPU time 35.42 seconds
Started Apr 15 01:27:21 PM PDT 24
Finished Apr 15 01:27:57 PM PDT 24
Peak memory 233000 kb
Host smart-3843c806-8a95-411e-af3f-cc4011e49d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783622294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2783622294
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2617663016
Short name T701
Test name
Test status
Simulation time 16567590 ps
CPU time 0.67 seconds
Started Apr 15 01:27:27 PM PDT 24
Finished Apr 15 01:27:28 PM PDT 24
Peak memory 205776 kb
Host smart-f267e388-b606-45c6-b51d-a8e4b21bd6ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617663016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2617663016
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2910412916
Short name T677
Test name
Test status
Simulation time 22382003 ps
CPU time 0.75 seconds
Started Apr 15 01:27:21 PM PDT 24
Finished Apr 15 01:27:22 PM PDT 24
Peak memory 206980 kb
Host smart-0ca8e8c2-4e41-4c1b-bbfb-1efb1ab94b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910412916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2910412916
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.428256221
Short name T82
Test name
Test status
Simulation time 3662276329 ps
CPU time 29.38 seconds
Started Apr 15 01:27:25 PM PDT 24
Finished Apr 15 01:27:55 PM PDT 24
Peak memory 249468 kb
Host smart-edd6e892-fb29-48a8-b960-33f9c963417c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428256221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.428256221
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3148047995
Short name T720
Test name
Test status
Simulation time 3622327538 ps
CPU time 16.8 seconds
Started Apr 15 01:27:27 PM PDT 24
Finished Apr 15 01:27:44 PM PDT 24
Peak memory 232580 kb
Host smart-b061369f-232e-441a-b06c-e75bde60c663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148047995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3148047995
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2952602068
Short name T430
Test name
Test status
Simulation time 1280072735 ps
CPU time 10.86 seconds
Started Apr 15 01:27:56 PM PDT 24
Finished Apr 15 01:28:07 PM PDT 24
Peak memory 221944 kb
Host smart-ad827649-e310-43ee-890d-ee5d7a701b44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2952602068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2952602068
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2773638705
Short name T507
Test name
Test status
Simulation time 153785137 ps
CPU time 0.95 seconds
Started Apr 15 01:27:32 PM PDT 24
Finished Apr 15 01:27:33 PM PDT 24
Peak memory 206768 kb
Host smart-73f557a1-1e1e-4b6c-a333-7ac78ae62a1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773638705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2773638705
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2432549807
Short name T650
Test name
Test status
Simulation time 5975094496 ps
CPU time 24.35 seconds
Started Apr 15 01:27:23 PM PDT 24
Finished Apr 15 01:27:48 PM PDT 24
Peak memory 216596 kb
Host smart-3ed70cc7-f192-4f8d-b5e4-d79944ccc5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432549807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2432549807
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3690484689
Short name T670
Test name
Test status
Simulation time 937394310 ps
CPU time 3.13 seconds
Started Apr 15 01:27:22 PM PDT 24
Finished Apr 15 01:27:26 PM PDT 24
Peak memory 216544 kb
Host smart-a17796fd-e2d7-41a7-8dbd-3aef2c638e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690484689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3690484689
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1395902406
Short name T463
Test name
Test status
Simulation time 117212915 ps
CPU time 1.39 seconds
Started Apr 15 01:27:21 PM PDT 24
Finished Apr 15 01:27:23 PM PDT 24
Peak memory 216576 kb
Host smart-ff26321f-467c-4e95-8506-eae450c4a182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395902406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1395902406
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2737334554
Short name T452
Test name
Test status
Simulation time 202454023 ps
CPU time 0.9 seconds
Started Apr 15 01:27:23 PM PDT 24
Finished Apr 15 01:27:24 PM PDT 24
Peak memory 206900 kb
Host smart-0b77cc5a-c990-4672-88c1-08483cefb13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737334554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2737334554
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1729895723
Short name T26
Test name
Test status
Simulation time 132930305 ps
CPU time 2.81 seconds
Started Apr 15 01:27:25 PM PDT 24
Finished Apr 15 01:27:28 PM PDT 24
Peak memory 218788 kb
Host smart-6aa0d7ea-f912-425c-8840-8578a541dfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729895723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1729895723
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.865621295
Short name T476
Test name
Test status
Simulation time 40469553 ps
CPU time 0.67 seconds
Started Apr 15 01:27:46 PM PDT 24
Finished Apr 15 01:27:47 PM PDT 24
Peak memory 204828 kb
Host smart-587d67a2-b3dd-4b92-83ed-ddb578d98dda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865621295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.865621295
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.102488840
Short name T11
Test name
Test status
Simulation time 1889809125 ps
CPU time 6.52 seconds
Started Apr 15 01:27:42 PM PDT 24
Finished Apr 15 01:27:48 PM PDT 24
Peak memory 224376 kb
Host smart-95b426bc-e24b-4f82-a97a-f628ef686dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102488840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.102488840
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1272348767
Short name T517
Test name
Test status
Simulation time 45808205 ps
CPU time 0.8 seconds
Started Apr 15 01:27:29 PM PDT 24
Finished Apr 15 01:27:30 PM PDT 24
Peak memory 205560 kb
Host smart-a7bfbf72-a662-4bff-a451-ec0b45e8043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272348767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1272348767
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3523348754
Short name T559
Test name
Test status
Simulation time 6294736579 ps
CPU time 32.17 seconds
Started Apr 15 01:27:42 PM PDT 24
Finished Apr 15 01:28:15 PM PDT 24
Peak memory 237108 kb
Host smart-beb95683-8114-4926-b14b-14ab710d95f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523348754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3523348754
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3910547805
Short name T226
Test name
Test status
Simulation time 180937887 ps
CPU time 3.5 seconds
Started Apr 15 01:27:38 PM PDT 24
Finished Apr 15 01:27:42 PM PDT 24
Peak memory 218840 kb
Host smart-c4d565bf-f670-4f66-97b6-63dbdf1a8d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910547805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3910547805
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3959360645
Short name T240
Test name
Test status
Simulation time 1131970437 ps
CPU time 7.89 seconds
Started Apr 15 01:27:34 PM PDT 24
Finished Apr 15 01:27:43 PM PDT 24
Peak memory 224408 kb
Host smart-ded5ad3d-7340-4b5f-babb-ef1d68bdff8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959360645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3959360645
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3966851092
Short name T645
Test name
Test status
Simulation time 2562382959 ps
CPU time 6.33 seconds
Started Apr 15 01:27:43 PM PDT 24
Finished Apr 15 01:27:50 PM PDT 24
Peak memory 222992 kb
Host smart-91f486d2-2988-434d-8feb-00b6038d2eec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3966851092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3966851092
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.766942472
Short name T346
Test name
Test status
Simulation time 75052532 ps
CPU time 1.24 seconds
Started Apr 15 01:27:45 PM PDT 24
Finished Apr 15 01:27:47 PM PDT 24
Peak memory 207308 kb
Host smart-11c269b7-8e9a-4616-b73f-4a807c81c89d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766942472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.766942472
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.26771923
Short name T378
Test name
Test status
Simulation time 70206012160 ps
CPU time 64.12 seconds
Started Apr 15 01:27:35 PM PDT 24
Finished Apr 15 01:28:39 PM PDT 24
Peak memory 216580 kb
Host smart-65121598-6851-4c7a-9b11-0bac37fc936c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26771923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.26771923
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3482185340
Short name T556
Test name
Test status
Simulation time 16682672513 ps
CPU time 16.41 seconds
Started Apr 15 01:27:33 PM PDT 24
Finished Apr 15 01:27:50 PM PDT 24
Peak memory 216328 kb
Host smart-1febaa37-68d1-4ae9-a863-240010117847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482185340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3482185340
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3968794446
Short name T595
Test name
Test status
Simulation time 45508991 ps
CPU time 1.08 seconds
Started Apr 15 01:27:37 PM PDT 24
Finished Apr 15 01:27:38 PM PDT 24
Peak memory 208104 kb
Host smart-03c6c7b1-ef81-4fee-831f-1191a6a4ac11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968794446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3968794446
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3594054821
Short name T456
Test name
Test status
Simulation time 213372375 ps
CPU time 0.74 seconds
Started Apr 15 01:27:33 PM PDT 24
Finished Apr 15 01:27:34 PM PDT 24
Peak memory 205856 kb
Host smart-08430166-5a9a-4e84-bcb6-6a88397e400a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594054821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3594054821
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3444635134
Short name T417
Test name
Test status
Simulation time 41757581 ps
CPU time 0.7 seconds
Started Apr 15 01:27:58 PM PDT 24
Finished Apr 15 01:27:59 PM PDT 24
Peak memory 205744 kb
Host smart-c418e700-cd65-43bb-ac30-e058bb451777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444635134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3444635134
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2048542212
Short name T467
Test name
Test status
Simulation time 30903673 ps
CPU time 0.75 seconds
Started Apr 15 01:27:47 PM PDT 24
Finished Apr 15 01:27:48 PM PDT 24
Peak memory 205640 kb
Host smart-fcd1e37d-9ff2-4f35-b243-101309b985d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048542212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2048542212
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3544257162
Short name T620
Test name
Test status
Simulation time 1977331291 ps
CPU time 19.37 seconds
Started Apr 15 01:27:53 PM PDT 24
Finished Apr 15 01:28:13 PM PDT 24
Peak memory 249340 kb
Host smart-25a5b7df-f7e5-4118-ba0d-50464e6f164e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544257162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3544257162
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3263301442
Short name T629
Test name
Test status
Simulation time 1763355700 ps
CPU time 19.06 seconds
Started Apr 15 01:27:53 PM PDT 24
Finished Apr 15 01:28:12 PM PDT 24
Peak memory 218624 kb
Host smart-b185fc64-5317-404e-a13c-24f30b90f44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263301442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3263301442
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1612797479
Short name T176
Test name
Test status
Simulation time 88182640204 ps
CPU time 86.71 seconds
Started Apr 15 01:27:59 PM PDT 24
Finished Apr 15 01:29:26 PM PDT 24
Peak memory 232628 kb
Host smart-6a16fa4d-fb1c-4979-beb5-3773b32ac110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612797479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1612797479
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1509542180
Short name T258
Test name
Test status
Simulation time 1215274085 ps
CPU time 5.6 seconds
Started Apr 15 01:27:52 PM PDT 24
Finished Apr 15 01:27:58 PM PDT 24
Peak memory 224396 kb
Host smart-124847b6-c71b-407c-af9d-167c5c4af658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509542180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1509542180
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.4098405641
Short name T545
Test name
Test status
Simulation time 517220383 ps
CPU time 4.53 seconds
Started Apr 15 01:27:54 PM PDT 24
Finished Apr 15 01:27:59 PM PDT 24
Peak memory 219956 kb
Host smart-d2341b5f-ca43-4fd7-9c04-a06565b8068f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4098405641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.4098405641
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3522401857
Short name T376
Test name
Test status
Simulation time 23489036979 ps
CPU time 17.36 seconds
Started Apr 15 01:27:52 PM PDT 24
Finished Apr 15 01:28:09 PM PDT 24
Peak memory 216616 kb
Host smart-b57a79a1-9738-442c-b5ad-962526f59e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522401857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3522401857
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2486820702
Short name T408
Test name
Test status
Simulation time 1095705358 ps
CPU time 6.41 seconds
Started Apr 15 01:27:44 PM PDT 24
Finished Apr 15 01:27:51 PM PDT 24
Peak memory 216516 kb
Host smart-ec11498e-10da-48cc-b3f2-f56877f5e2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486820702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2486820702
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.10214404
Short name T420
Test name
Test status
Simulation time 537381002 ps
CPU time 4.25 seconds
Started Apr 15 01:27:52 PM PDT 24
Finished Apr 15 01:27:56 PM PDT 24
Peak memory 216604 kb
Host smart-0c72eb94-a569-4c8b-8629-c4c24717809b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10214404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.10214404
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1219010229
Short name T468
Test name
Test status
Simulation time 514336614 ps
CPU time 0.78 seconds
Started Apr 15 01:27:50 PM PDT 24
Finished Apr 15 01:27:52 PM PDT 24
Peak memory 205884 kb
Host smart-2dd4597b-a4ac-4005-9d45-f2c89b2c7134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219010229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1219010229
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3473224415
Short name T276
Test name
Test status
Simulation time 2149438304 ps
CPU time 3.86 seconds
Started Apr 15 01:27:56 PM PDT 24
Finished Apr 15 01:28:00 PM PDT 24
Peak memory 223244 kb
Host smart-217026d4-7827-4869-a65f-53ef6ccd1150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473224415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3473224415
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3133860547
Short name T557
Test name
Test status
Simulation time 14815670 ps
CPU time 0.7 seconds
Started Apr 15 01:28:12 PM PDT 24
Finished Apr 15 01:28:13 PM PDT 24
Peak memory 205392 kb
Host smart-d7abf82b-bd30-4f7e-a042-5a2340771b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133860547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3133860547
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2180070288
Short name T195
Test name
Test status
Simulation time 5235918476 ps
CPU time 16.04 seconds
Started Apr 15 01:28:05 PM PDT 24
Finished Apr 15 01:28:22 PM PDT 24
Peak memory 223628 kb
Host smart-825370a3-a822-4e6a-af45-e59577628cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180070288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2180070288
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4081130284
Short name T615
Test name
Test status
Simulation time 26354566 ps
CPU time 0.8 seconds
Started Apr 15 01:28:01 PM PDT 24
Finished Apr 15 01:28:02 PM PDT 24
Peak memory 206648 kb
Host smart-7331107d-61bb-4aed-a7a9-1060bdab1db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081130284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4081130284
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.454474873
Short name T285
Test name
Test status
Simulation time 43937769418 ps
CPU time 143.97 seconds
Started Apr 15 01:28:10 PM PDT 24
Finished Apr 15 01:30:34 PM PDT 24
Peak memory 252664 kb
Host smart-84b4693d-a2f7-4c85-b08c-ba5f732d83e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454474873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.454474873
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1680171068
Short name T165
Test name
Test status
Simulation time 1351303471 ps
CPU time 14.73 seconds
Started Apr 15 01:28:05 PM PDT 24
Finished Apr 15 01:28:20 PM PDT 24
Peak memory 223144 kb
Host smart-dec056d6-e47e-4c0d-aa52-73bdf95ea69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680171068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1680171068
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2320443422
Short name T257
Test name
Test status
Simulation time 7994644988 ps
CPU time 76.14 seconds
Started Apr 15 01:28:06 PM PDT 24
Finished Apr 15 01:29:22 PM PDT 24
Peak memory 232992 kb
Host smart-7a78bcf6-c8aa-42b6-a8cd-7e5b43425b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320443422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2320443422
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1662796444
Short name T100
Test name
Test status
Simulation time 1881468413 ps
CPU time 13.04 seconds
Started Apr 15 01:28:03 PM PDT 24
Finished Apr 15 01:28:16 PM PDT 24
Peak memory 224796 kb
Host smart-d00f4445-e25a-44f5-b1ff-188e8bcb274e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662796444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1662796444
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1020229905
Short name T373
Test name
Test status
Simulation time 3315953360 ps
CPU time 5.81 seconds
Started Apr 15 01:28:04 PM PDT 24
Finished Apr 15 01:28:10 PM PDT 24
Peak memory 218836 kb
Host smart-0b68a468-d0cd-4a68-98b0-d1648499d44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020229905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1020229905
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3842129485
Short name T552
Test name
Test status
Simulation time 3144865314 ps
CPU time 10.25 seconds
Started Apr 15 01:28:10 PM PDT 24
Finished Apr 15 01:28:20 PM PDT 24
Peak memory 219428 kb
Host smart-65bdfb9b-9459-4365-a06a-0d29e28d1da2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3842129485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3842129485
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3499962187
Short name T573
Test name
Test status
Simulation time 11961878214 ps
CPU time 58.31 seconds
Started Apr 15 01:27:58 PM PDT 24
Finished Apr 15 01:28:57 PM PDT 24
Peak memory 216576 kb
Host smart-99cdb4fd-22c1-4814-a0bd-a468daef544b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499962187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3499962187
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3429908973
Short name T485
Test name
Test status
Simulation time 9016090750 ps
CPU time 26.13 seconds
Started Apr 15 01:27:59 PM PDT 24
Finished Apr 15 01:28:25 PM PDT 24
Peak memory 216656 kb
Host smart-0316278e-81c1-4a92-89a4-b31258536b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429908973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3429908973
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.604873252
Short name T436
Test name
Test status
Simulation time 435903819 ps
CPU time 3.78 seconds
Started Apr 15 01:28:00 PM PDT 24
Finished Apr 15 01:28:04 PM PDT 24
Peak memory 216584 kb
Host smart-20b9aa15-8d09-4f54-8fad-1a1d17bba720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604873252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.604873252
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3298683667
Short name T411
Test name
Test status
Simulation time 73231259 ps
CPU time 0.95 seconds
Started Apr 15 01:27:59 PM PDT 24
Finished Apr 15 01:28:00 PM PDT 24
Peak memory 205452 kb
Host smart-49013a1b-f7c4-4782-ad5e-2f936f4db4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298683667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3298683667
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2524061895
Short name T315
Test name
Test status
Simulation time 51807103 ps
CPU time 2.31 seconds
Started Apr 15 01:28:05 PM PDT 24
Finished Apr 15 01:28:07 PM PDT 24
Peak memory 216604 kb
Host smart-eba48dda-4fb7-4a05-b332-068ab925916d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524061895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2524061895
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2379618863
Short name T699
Test name
Test status
Simulation time 29121148 ps
CPU time 0.75 seconds
Started Apr 15 01:28:24 PM PDT 24
Finished Apr 15 01:28:25 PM PDT 24
Peak memory 205408 kb
Host smart-fd8c241b-8c7c-438f-93be-b3ce702c441b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379618863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2379618863
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3247348467
Short name T521
Test name
Test status
Simulation time 81742399 ps
CPU time 0.74 seconds
Started Apr 15 01:28:12 PM PDT 24
Finished Apr 15 01:28:14 PM PDT 24
Peak memory 206544 kb
Host smart-a6dce021-c51e-44bd-9065-a3c578a9e8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247348467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3247348467
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3103528502
Short name T654
Test name
Test status
Simulation time 6238660484 ps
CPU time 36.82 seconds
Started Apr 15 01:28:23 PM PDT 24
Finished Apr 15 01:29:00 PM PDT 24
Peak memory 251828 kb
Host smart-cebaac2c-23fe-4fa2-8290-2e347a72e603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103528502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3103528502
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1476490191
Short name T312
Test name
Test status
Simulation time 1495589068 ps
CPU time 8.33 seconds
Started Apr 15 01:28:18 PM PDT 24
Finished Apr 15 01:28:27 PM PDT 24
Peak memory 235448 kb
Host smart-e2ce4dc5-5dc4-441a-a0ba-6d2d5afd1114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476490191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1476490191
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1303266638
Short name T232
Test name
Test status
Simulation time 762115870 ps
CPU time 8.34 seconds
Started Apr 15 01:28:23 PM PDT 24
Finished Apr 15 01:28:32 PM PDT 24
Peak memory 223556 kb
Host smart-c113c621-40cc-4e76-b00c-5decb593b4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303266638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1303266638
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2402259376
Short name T603
Test name
Test status
Simulation time 544694911 ps
CPU time 6.29 seconds
Started Apr 15 01:28:22 PM PDT 24
Finished Apr 15 01:28:29 PM PDT 24
Peak memory 219000 kb
Host smart-e36974df-b5b0-4e1d-9770-2d2949e0f2a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2402259376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2402259376
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2952701644
Short name T377
Test name
Test status
Simulation time 12762046704 ps
CPU time 19.2 seconds
Started Apr 15 01:28:17 PM PDT 24
Finished Apr 15 01:28:37 PM PDT 24
Peak memory 216736 kb
Host smart-cbd4a304-fa7e-4898-9baa-30baff6231c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952701644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2952701644
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.346643005
Short name T478
Test name
Test status
Simulation time 21018993409 ps
CPU time 8.48 seconds
Started Apr 15 01:28:14 PM PDT 24
Finished Apr 15 01:28:22 PM PDT 24
Peak memory 216540 kb
Host smart-bedf6c58-cc95-4e6e-b72d-7aa819800f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346643005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.346643005
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3537240717
Short name T57
Test name
Test status
Simulation time 146179359 ps
CPU time 1.03 seconds
Started Apr 15 01:28:19 PM PDT 24
Finished Apr 15 01:28:20 PM PDT 24
Peak memory 207052 kb
Host smart-e57da6b9-51a1-4c36-a055-8ec7651ead5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537240717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3537240717
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.491993309
Short name T530
Test name
Test status
Simulation time 166289672 ps
CPU time 1.07 seconds
Started Apr 15 01:28:19 PM PDT 24
Finished Apr 15 01:28:21 PM PDT 24
Peak memory 206912 kb
Host smart-3c7f5f07-89a9-40d5-bff4-94ae8c4be4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491993309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.491993309
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1071154033
Short name T316
Test name
Test status
Simulation time 665718437 ps
CPU time 4.57 seconds
Started Apr 15 01:28:20 PM PDT 24
Finished Apr 15 01:28:25 PM PDT 24
Peak memory 219032 kb
Host smart-02f6eea1-c204-4b22-9952-75e36a6c9a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071154033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1071154033
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2253192727
Short name T669
Test name
Test status
Simulation time 14409119 ps
CPU time 0.69 seconds
Started Apr 15 01:28:36 PM PDT 24
Finished Apr 15 01:28:37 PM PDT 24
Peak memory 205380 kb
Host smart-02f40a85-2c3a-4eee-aa3f-e2a6b823fab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253192727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2253192727
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2968010909
Short name T25
Test name
Test status
Simulation time 1606308308 ps
CPU time 17.35 seconds
Started Apr 15 01:28:34 PM PDT 24
Finished Apr 15 01:28:52 PM PDT 24
Peak memory 223120 kb
Host smart-fb7082a1-39c8-4888-a85f-f2ce85eb999d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968010909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2968010909
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3990617225
Short name T636
Test name
Test status
Simulation time 66275472 ps
CPU time 0.75 seconds
Started Apr 15 01:28:25 PM PDT 24
Finished Apr 15 01:28:26 PM PDT 24
Peak memory 206656 kb
Host smart-688aa230-5793-44fd-a22b-178271b5cca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990617225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3990617225
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2918183816
Short name T114
Test name
Test status
Simulation time 348413660 ps
CPU time 4.86 seconds
Started Apr 15 01:28:32 PM PDT 24
Finished Apr 15 01:28:37 PM PDT 24
Peak memory 220808 kb
Host smart-7dd901a3-fc96-4286-a805-64fc6263592b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918183816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2918183816
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1054468918
Short name T227
Test name
Test status
Simulation time 15044505445 ps
CPU time 21.96 seconds
Started Apr 15 01:28:31 PM PDT 24
Finished Apr 15 01:28:54 PM PDT 24
Peak memory 224452 kb
Host smart-d3be7823-2f83-458f-a5c2-f9388b6ad0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054468918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1054468918
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3549104811
Short name T558
Test name
Test status
Simulation time 704693006 ps
CPU time 4.36 seconds
Started Apr 15 01:28:33 PM PDT 24
Finished Apr 15 01:28:38 PM PDT 24
Peak memory 223100 kb
Host smart-5ecd30c5-3bc1-415f-8515-32bb6c80ba3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3549104811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3549104811
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1311263018
Short name T383
Test name
Test status
Simulation time 4035365644 ps
CPU time 22.15 seconds
Started Apr 15 01:28:28 PM PDT 24
Finished Apr 15 01:28:50 PM PDT 24
Peak memory 216636 kb
Host smart-e1f1b7ed-a4e8-454a-b1a2-9a26118d6fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311263018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1311263018
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3051163384
Short name T569
Test name
Test status
Simulation time 3596580002 ps
CPU time 4.26 seconds
Started Apr 15 01:28:26 PM PDT 24
Finished Apr 15 01:28:30 PM PDT 24
Peak memory 216660 kb
Host smart-2b30bfc2-6650-47cc-b063-aa6dcdd38054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051163384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3051163384
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3446651126
Short name T686
Test name
Test status
Simulation time 180284000 ps
CPU time 1.1 seconds
Started Apr 15 01:28:25 PM PDT 24
Finished Apr 15 01:28:27 PM PDT 24
Peak memory 207972 kb
Host smart-49644003-39f2-4b5b-849f-31c4c89db1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446651126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3446651126
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.634614600
Short name T54
Test name
Test status
Simulation time 72564733 ps
CPU time 0.7 seconds
Started Apr 15 01:28:26 PM PDT 24
Finished Apr 15 01:28:27 PM PDT 24
Peak memory 205844 kb
Host smart-35413d75-7567-41cb-9287-a48110d0409a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634614600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.634614600
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1036413377
Short name T231
Test name
Test status
Simulation time 134032543 ps
CPU time 2.3 seconds
Started Apr 15 01:28:34 PM PDT 24
Finished Apr 15 01:28:37 PM PDT 24
Peak memory 216296 kb
Host smart-e6307bf8-1b57-4bd9-9803-5dda4017a72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036413377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1036413377
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.4051482523
Short name T738
Test name
Test status
Simulation time 13153119 ps
CPU time 0.7 seconds
Started Apr 15 01:22:55 PM PDT 24
Finished Apr 15 01:22:56 PM PDT 24
Peak memory 205252 kb
Host smart-9b93dbe8-7be8-45a8-a363-45eab1e0a69e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051482523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.4
051482523
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.19769408
Short name T183
Test name
Test status
Simulation time 55017770037 ps
CPU time 30.96 seconds
Started Apr 15 01:22:51 PM PDT 24
Finished Apr 15 01:23:23 PM PDT 24
Peak memory 224208 kb
Host smart-09395ef0-3f5a-49ed-8290-9923e6def15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19769408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.19769408
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2934234674
Short name T737
Test name
Test status
Simulation time 265404494 ps
CPU time 0.75 seconds
Started Apr 15 01:22:48 PM PDT 24
Finished Apr 15 01:22:49 PM PDT 24
Peak memory 206908 kb
Host smart-5d0add2a-9c4d-4f42-a62f-cee22c8c25f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934234674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2934234674
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2971928793
Short name T528
Test name
Test status
Simulation time 73633213 ps
CPU time 2.4 seconds
Started Apr 15 01:22:53 PM PDT 24
Finished Apr 15 01:22:56 PM PDT 24
Peak memory 218752 kb
Host smart-6c578898-af23-4e09-bb00-f7a4c1a4086f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971928793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2971928793
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3527639237
Short name T305
Test name
Test status
Simulation time 3445464198 ps
CPU time 14.12 seconds
Started Apr 15 01:22:53 PM PDT 24
Finished Apr 15 01:23:07 PM PDT 24
Peak memory 233548 kb
Host smart-86836fd2-276c-44b9-8d3f-030653580589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527639237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3527639237
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.4003460876
Short name T568
Test name
Test status
Simulation time 40345153 ps
CPU time 1.05 seconds
Started Apr 15 01:22:49 PM PDT 24
Finished Apr 15 01:22:50 PM PDT 24
Peak memory 216984 kb
Host smart-65bdd8d7-faf2-4fc0-b7d1-e72abcbfde8b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003460876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.4003460876
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2203883679
Short name T275
Test name
Test status
Simulation time 4850480662 ps
CPU time 10.62 seconds
Started Apr 15 01:22:52 PM PDT 24
Finished Apr 15 01:23:03 PM PDT 24
Peak memory 216908 kb
Host smart-d863e2b9-110f-474d-93a4-aed0a626dc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203883679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2203883679
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3474997784
Short name T683
Test name
Test status
Simulation time 758453194 ps
CPU time 3.51 seconds
Started Apr 15 01:22:55 PM PDT 24
Finished Apr 15 01:22:59 PM PDT 24
Peak memory 222668 kb
Host smart-aa3011ec-ddff-4d3c-9f0e-fb92441a79e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3474997784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3474997784
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3334978763
Short name T43
Test name
Test status
Simulation time 154403627 ps
CPU time 1.03 seconds
Started Apr 15 01:22:55 PM PDT 24
Finished Apr 15 01:22:56 PM PDT 24
Peak memory 235452 kb
Host smart-d44c0df7-a372-472c-a53c-bdc22e736467
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334978763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3334978763
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1064777726
Short name T714
Test name
Test status
Simulation time 8036451140 ps
CPU time 24.14 seconds
Started Apr 15 01:22:50 PM PDT 24
Finished Apr 15 01:23:15 PM PDT 24
Peak memory 216588 kb
Host smart-0172f31f-3e71-49e9-a623-19ceaf90c9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064777726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1064777726
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3117058019
Short name T611
Test name
Test status
Simulation time 10436738838 ps
CPU time 20.06 seconds
Started Apr 15 01:22:46 PM PDT 24
Finished Apr 15 01:23:06 PM PDT 24
Peak memory 216648 kb
Host smart-3033a6b3-1326-4ab3-b481-11c347ac98a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117058019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3117058019
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1667648026
Short name T587
Test name
Test status
Simulation time 181905638 ps
CPU time 3.14 seconds
Started Apr 15 01:22:50 PM PDT 24
Finished Apr 15 01:22:54 PM PDT 24
Peak memory 216568 kb
Host smart-c65fd8c4-1cb3-4c10-a7a2-a0d1b0a9be37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667648026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1667648026
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.502751238
Short name T14
Test name
Test status
Simulation time 42844707 ps
CPU time 0.8 seconds
Started Apr 15 01:22:52 PM PDT 24
Finished Apr 15 01:22:53 PM PDT 24
Peak memory 205868 kb
Host smart-9eee0739-db2f-4f56-ace3-73d8ef6f4838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502751238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.502751238
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.643403888
Short name T716
Test name
Test status
Simulation time 22221441 ps
CPU time 0.66 seconds
Started Apr 15 01:28:53 PM PDT 24
Finished Apr 15 01:28:54 PM PDT 24
Peak memory 205764 kb
Host smart-c100ea59-58c2-4d6d-a2be-1c3381f663fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643403888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.643403888
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1913391002
Short name T705
Test name
Test status
Simulation time 63551498 ps
CPU time 0.74 seconds
Started Apr 15 01:28:39 PM PDT 24
Finished Apr 15 01:28:40 PM PDT 24
Peak memory 206644 kb
Host smart-47ae722b-6711-4c06-9d3e-0a6804c0d9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913391002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1913391002
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4071130433
Short name T570
Test name
Test status
Simulation time 3725931832 ps
CPU time 56.65 seconds
Started Apr 15 01:28:48 PM PDT 24
Finished Apr 15 01:29:45 PM PDT 24
Peak memory 249164 kb
Host smart-20883232-e1c8-4f03-9f0c-f1102db1b4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071130433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4071130433
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1197756273
Short name T238
Test name
Test status
Simulation time 392426889 ps
CPU time 7.28 seconds
Started Apr 15 01:28:45 PM PDT 24
Finished Apr 15 01:28:53 PM PDT 24
Peak memory 218652 kb
Host smart-ef9ba5c0-583f-405d-ad00-8dddac265bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197756273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1197756273
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.332456848
Short name T244
Test name
Test status
Simulation time 25054237215 ps
CPU time 34.18 seconds
Started Apr 15 01:28:44 PM PDT 24
Finished Apr 15 01:29:18 PM PDT 24
Peak memory 237876 kb
Host smart-a8cf07a0-81d8-40ac-a53b-0e776d0f790d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332456848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.332456848
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2665714853
Short name T717
Test name
Test status
Simulation time 1280330635 ps
CPU time 15.14 seconds
Started Apr 15 01:28:49 PM PDT 24
Finished Apr 15 01:29:05 PM PDT 24
Peak memory 222412 kb
Host smart-6617c666-4af6-45c6-a4f3-0a1ebabce176
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2665714853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2665714853
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.405672445
Short name T579
Test name
Test status
Simulation time 1148183053 ps
CPU time 17.74 seconds
Started Apr 15 01:28:40 PM PDT 24
Finished Apr 15 01:28:58 PM PDT 24
Peak memory 216468 kb
Host smart-0d6c9a0a-7d3a-4a6d-9453-2f60eefa4987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405672445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.405672445
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3153731314
Short name T674
Test name
Test status
Simulation time 18869178216 ps
CPU time 11.5 seconds
Started Apr 15 01:28:40 PM PDT 24
Finished Apr 15 01:28:52 PM PDT 24
Peak memory 216580 kb
Host smart-36c23047-740f-4dd1-bf7e-39886d01b8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153731314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3153731314
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3957294754
Short name T401
Test name
Test status
Simulation time 37227907 ps
CPU time 0.86 seconds
Started Apr 15 01:28:44 PM PDT 24
Finished Apr 15 01:28:46 PM PDT 24
Peak memory 206484 kb
Host smart-25d57c3d-15cf-4982-9621-646d3a320ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957294754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3957294754
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.4206365502
Short name T597
Test name
Test status
Simulation time 209258604 ps
CPU time 0.89 seconds
Started Apr 15 01:28:44 PM PDT 24
Finished Apr 15 01:28:45 PM PDT 24
Peak memory 206872 kb
Host smart-1397a4a4-5540-43fb-a5f0-6ae1e6e8cb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206365502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.4206365502
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.374411697
Short name T359
Test name
Test status
Simulation time 884964402 ps
CPU time 6.18 seconds
Started Apr 15 01:28:49 PM PDT 24
Finished Apr 15 01:28:56 PM PDT 24
Peak memory 217584 kb
Host smart-4716c055-d610-4d99-9761-16f941094ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374411697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.374411697
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2199185846
Short name T458
Test name
Test status
Simulation time 16365797 ps
CPU time 0.74 seconds
Started Apr 15 01:29:12 PM PDT 24
Finished Apr 15 01:29:14 PM PDT 24
Peak memory 205424 kb
Host smart-c618bf94-8c5c-481b-a1e6-c21533bc567b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199185846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2199185846
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3512352950
Short name T262
Test name
Test status
Simulation time 662035872 ps
CPU time 8.28 seconds
Started Apr 15 01:29:00 PM PDT 24
Finished Apr 15 01:29:09 PM PDT 24
Peak memory 223184 kb
Host smart-78ddc7c9-070b-434b-9daf-f0af21b2bbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512352950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3512352950
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2721386277
Short name T713
Test name
Test status
Simulation time 27719692 ps
CPU time 0.76 seconds
Started Apr 15 01:28:53 PM PDT 24
Finished Apr 15 01:28:55 PM PDT 24
Peak memory 206632 kb
Host smart-4bb5970f-16f3-4737-b7c3-d0f5df4574a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721386277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2721386277
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1189871766
Short name T292
Test name
Test status
Simulation time 1788216187 ps
CPU time 35.26 seconds
Started Apr 15 01:29:02 PM PDT 24
Finished Apr 15 01:29:38 PM PDT 24
Peak memory 224496 kb
Host smart-a4e13817-460a-412d-9640-9d60cd9995ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189871766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1189871766
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4180271481
Short name T113
Test name
Test status
Simulation time 5949719038 ps
CPU time 7.67 seconds
Started Apr 15 01:28:56 PM PDT 24
Finished Apr 15 01:29:04 PM PDT 24
Peak memory 217696 kb
Host smart-5b33a700-35dc-4d6e-a7be-0a0dc515ad18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180271481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4180271481
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1954601439
Short name T85
Test name
Test status
Simulation time 20631177145 ps
CPU time 22.22 seconds
Started Apr 15 01:28:59 PM PDT 24
Finished Apr 15 01:29:21 PM PDT 24
Peak memory 224728 kb
Host smart-c1371214-c537-4fd8-84d0-ea12e628e09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954601439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1954601439
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2345127126
Short name T469
Test name
Test status
Simulation time 163922685 ps
CPU time 3.54 seconds
Started Apr 15 01:29:01 PM PDT 24
Finished Apr 15 01:29:05 PM PDT 24
Peak memory 220040 kb
Host smart-01e108ee-8ff5-4bc7-b479-fba0b8185442
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2345127126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2345127126
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.90334150
Short name T382
Test name
Test status
Simulation time 4966489626 ps
CPU time 36.38 seconds
Started Apr 15 01:28:59 PM PDT 24
Finished Apr 15 01:29:36 PM PDT 24
Peak memory 216612 kb
Host smart-07c56b1b-9b93-4b3e-aa4f-bda399141b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90334150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.90334150
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2061355669
Short name T565
Test name
Test status
Simulation time 2782305181 ps
CPU time 12.03 seconds
Started Apr 15 01:28:59 PM PDT 24
Finished Apr 15 01:29:11 PM PDT 24
Peak memory 216560 kb
Host smart-667e8b50-a1a0-466b-ab76-a1660badde80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061355669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2061355669
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2674774475
Short name T741
Test name
Test status
Simulation time 447356111 ps
CPU time 6.72 seconds
Started Apr 15 01:28:58 PM PDT 24
Finished Apr 15 01:29:05 PM PDT 24
Peak memory 216532 kb
Host smart-a65d8659-3f9f-451b-913a-f680baad473e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674774475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2674774475
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.465657282
Short name T416
Test name
Test status
Simulation time 93080776 ps
CPU time 0.76 seconds
Started Apr 15 01:28:57 PM PDT 24
Finished Apr 15 01:28:58 PM PDT 24
Peak memory 205812 kb
Host smart-d26d9238-6b32-4af1-82ac-8b681fecac86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465657282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.465657282
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.4165714923
Short name T268
Test name
Test status
Simulation time 11424153179 ps
CPU time 18.09 seconds
Started Apr 15 01:29:02 PM PDT 24
Finished Apr 15 01:29:20 PM PDT 24
Peak memory 239728 kb
Host smart-858f9880-1408-45c0-8c81-55a5257d91ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165714923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.4165714923
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1978764266
Short name T410
Test name
Test status
Simulation time 78338592 ps
CPU time 0.71 seconds
Started Apr 15 01:29:24 PM PDT 24
Finished Apr 15 01:29:25 PM PDT 24
Peak memory 205432 kb
Host smart-e9fc8e8c-5f2c-4a36-8ba2-bbaf0db17ed6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978764266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1978764266
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2192915848
Short name T433
Test name
Test status
Simulation time 104372508 ps
CPU time 0.78 seconds
Started Apr 15 01:29:11 PM PDT 24
Finished Apr 15 01:29:12 PM PDT 24
Peak memory 206644 kb
Host smart-6374fb5e-0073-4c5d-9a57-4020a1c81ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192915848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2192915848
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2349453496
Short name T89
Test name
Test status
Simulation time 7490134882 ps
CPU time 23.73 seconds
Started Apr 15 01:29:20 PM PDT 24
Finished Apr 15 01:29:44 PM PDT 24
Peak memory 253784 kb
Host smart-110824f7-10cc-4b66-ba21-d6d4721543f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349453496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2349453496
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1199934188
Short name T254
Test name
Test status
Simulation time 427305550 ps
CPU time 5.56 seconds
Started Apr 15 01:29:19 PM PDT 24
Finished Apr 15 01:29:25 PM PDT 24
Peak memory 222060 kb
Host smart-933a28d7-45f3-45df-9274-b7bc6e234975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199934188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1199934188
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.743542326
Short name T229
Test name
Test status
Simulation time 220764345 ps
CPU time 2.48 seconds
Started Apr 15 01:29:24 PM PDT 24
Finished Apr 15 01:29:27 PM PDT 24
Peak memory 223196 kb
Host smart-54ab41ba-e1f4-4618-b3ea-a4f3803e35a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743542326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.743542326
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2529904358
Short name T300
Test name
Test status
Simulation time 818295892 ps
CPU time 3.25 seconds
Started Apr 15 01:29:12 PM PDT 24
Finished Apr 15 01:29:15 PM PDT 24
Peak memory 222200 kb
Host smart-07de4db2-73d6-4b48-b6e3-d86c9f40856e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529904358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2529904358
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2228380213
Short name T535
Test name
Test status
Simulation time 588499843 ps
CPU time 3.74 seconds
Started Apr 15 01:29:26 PM PDT 24
Finished Apr 15 01:29:30 PM PDT 24
Peak memory 220108 kb
Host smart-c9a991a8-71cf-4a14-9139-aaa47f664259
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2228380213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2228380213
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1553753543
Short name T596
Test name
Test status
Simulation time 30277397756 ps
CPU time 20.56 seconds
Started Apr 15 01:29:12 PM PDT 24
Finished Apr 15 01:29:33 PM PDT 24
Peak memory 220728 kb
Host smart-d92488a1-aaa1-43a1-8de8-f73a067f0914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553753543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1553753543
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.442945177
Short name T84
Test name
Test status
Simulation time 4291336000 ps
CPU time 11.96 seconds
Started Apr 15 01:29:10 PM PDT 24
Finished Apr 15 01:29:22 PM PDT 24
Peak memory 216596 kb
Host smart-93b557f4-5f5b-453a-9302-cbf32b1d517f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442945177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.442945177
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1022154899
Short name T471
Test name
Test status
Simulation time 17697316 ps
CPU time 0.91 seconds
Started Apr 15 01:29:12 PM PDT 24
Finished Apr 15 01:29:13 PM PDT 24
Peak memory 206872 kb
Host smart-566c9863-b814-4647-9cab-7f980942ca3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022154899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1022154899
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3666107282
Short name T724
Test name
Test status
Simulation time 107732860 ps
CPU time 0.99 seconds
Started Apr 15 01:29:13 PM PDT 24
Finished Apr 15 01:29:14 PM PDT 24
Peak memory 206908 kb
Host smart-205a0ce1-330b-4329-b443-b7462977437a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666107282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3666107282
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1465113592
Short name T222
Test name
Test status
Simulation time 10566121715 ps
CPU time 17.76 seconds
Started Apr 15 01:29:20 PM PDT 24
Finished Apr 15 01:29:38 PM PDT 24
Peak memory 219152 kb
Host smart-09677f41-fb2e-4b7a-a3e4-95e86ba12d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465113592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1465113592
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.567883144
Short name T697
Test name
Test status
Simulation time 46576672 ps
CPU time 0.69 seconds
Started Apr 15 01:29:42 PM PDT 24
Finished Apr 15 01:29:43 PM PDT 24
Peak memory 205380 kb
Host smart-a2f9e2a2-fbca-4fd1-bbfd-a54fd712ac20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567883144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.567883144
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3883608585
Short name T496
Test name
Test status
Simulation time 14790931 ps
CPU time 0.76 seconds
Started Apr 15 01:29:28 PM PDT 24
Finished Apr 15 01:29:30 PM PDT 24
Peak memory 205608 kb
Host smart-e603cb77-445b-4d55-a4f7-53ac44fed9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883608585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3883608585
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1259014340
Short name T296
Test name
Test status
Simulation time 28401159402 ps
CPU time 57.88 seconds
Started Apr 15 01:29:41 PM PDT 24
Finished Apr 15 01:30:39 PM PDT 24
Peak memory 235532 kb
Host smart-afa9b946-2358-4d40-b7ca-8672616bebb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259014340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1259014340
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.4027475391
Short name T252
Test name
Test status
Simulation time 17715506763 ps
CPU time 15.62 seconds
Started Apr 15 01:29:33 PM PDT 24
Finished Apr 15 01:29:49 PM PDT 24
Peak memory 224784 kb
Host smart-482dfa51-6cb2-4930-b709-fd9af064cdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027475391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.4027475391
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.964962740
Short name T495
Test name
Test status
Simulation time 210210265 ps
CPU time 3.22 seconds
Started Apr 15 01:29:36 PM PDT 24
Finished Apr 15 01:29:40 PM PDT 24
Peak memory 221356 kb
Host smart-868bba19-510e-4b04-8f28-aa74e23b2dd8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=964962740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.964962740
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1974249947
Short name T380
Test name
Test status
Simulation time 1818160644 ps
CPU time 15.04 seconds
Started Apr 15 01:29:28 PM PDT 24
Finished Apr 15 01:29:43 PM PDT 24
Peak memory 216584 kb
Host smart-fc9488d9-4aca-4feb-b30b-04ae6b9887af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974249947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1974249947
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2347605855
Short name T482
Test name
Test status
Simulation time 679122662 ps
CPU time 1.59 seconds
Started Apr 15 01:29:27 PM PDT 24
Finished Apr 15 01:29:29 PM PDT 24
Peak memory 206980 kb
Host smart-453c219f-789b-4d3f-b487-ea134654e77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347605855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2347605855
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.984338158
Short name T619
Test name
Test status
Simulation time 550280005 ps
CPU time 4.28 seconds
Started Apr 15 01:29:28 PM PDT 24
Finished Apr 15 01:29:32 PM PDT 24
Peak memory 216792 kb
Host smart-4e2cbda2-a232-43a8-baac-8265e4b63198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984338158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.984338158
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2773443704
Short name T421
Test name
Test status
Simulation time 62961914 ps
CPU time 0.71 seconds
Started Apr 15 01:29:29 PM PDT 24
Finished Apr 15 01:29:30 PM PDT 24
Peak memory 205856 kb
Host smart-f8f65c19-9751-466a-931a-74564d41bdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773443704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2773443704
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1963882450
Short name T314
Test name
Test status
Simulation time 4051128965 ps
CPU time 10.37 seconds
Started Apr 15 01:29:34 PM PDT 24
Finished Apr 15 01:29:45 PM PDT 24
Peak memory 216652 kb
Host smart-6b5f83e7-717c-4c51-b568-05d13d9bc2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963882450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1963882450
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2473831252
Short name T602
Test name
Test status
Simulation time 13302733 ps
CPU time 0.68 seconds
Started Apr 15 01:29:55 PM PDT 24
Finished Apr 15 01:29:56 PM PDT 24
Peak memory 205412 kb
Host smart-6b81d90e-38bb-408e-afd4-af44d6e39b65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473831252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2473831252
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2200107245
Short name T582
Test name
Test status
Simulation time 49810294 ps
CPU time 0.72 seconds
Started Apr 15 01:29:41 PM PDT 24
Finished Apr 15 01:29:42 PM PDT 24
Peak memory 205632 kb
Host smart-3a579af8-652e-474a-ade3-ae5d5a96cef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200107245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2200107245
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2268896808
Short name T291
Test name
Test status
Simulation time 2739774793 ps
CPU time 20.54 seconds
Started Apr 15 01:29:52 PM PDT 24
Finished Apr 15 01:30:13 PM PDT 24
Peak memory 241216 kb
Host smart-444a9995-a89a-459f-872c-7f254b615005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268896808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2268896808
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2004263796
Short name T360
Test name
Test status
Simulation time 25553899666 ps
CPU time 29.14 seconds
Started Apr 15 01:29:47 PM PDT 24
Finished Apr 15 01:30:16 PM PDT 24
Peak memory 223816 kb
Host smart-c9d284a8-598c-402a-a3a7-1011d423560d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004263796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2004263796
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3231027998
Short name T122
Test name
Test status
Simulation time 16178203422 ps
CPU time 43.45 seconds
Started Apr 15 01:29:47 PM PDT 24
Finished Apr 15 01:30:30 PM PDT 24
Peak memory 223156 kb
Host smart-7f905682-1635-41b0-bae3-b634dd67c7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231027998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3231027998
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2690170069
Short name T333
Test name
Test status
Simulation time 1257639813 ps
CPU time 7.63 seconds
Started Apr 15 01:29:46 PM PDT 24
Finished Apr 15 01:29:54 PM PDT 24
Peak memory 233000 kb
Host smart-16dc4a5e-043f-4ce5-92c3-b8ebbe47bbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690170069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2690170069
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3694504242
Short name T444
Test name
Test status
Simulation time 11655925715 ps
CPU time 13.65 seconds
Started Apr 15 01:29:54 PM PDT 24
Finished Apr 15 01:30:08 PM PDT 24
Peak memory 223052 kb
Host smart-519c1984-9c10-47a4-965f-03e802fa776b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3694504242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3694504242
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1960983013
Short name T591
Test name
Test status
Simulation time 3907791280 ps
CPU time 31.23 seconds
Started Apr 15 01:29:50 PM PDT 24
Finished Apr 15 01:30:22 PM PDT 24
Peak memory 216668 kb
Host smart-a0bb15c1-0c41-4c24-b224-d0f9d1debba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960983013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1960983013
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3159482572
Short name T493
Test name
Test status
Simulation time 2339223627 ps
CPU time 6.84 seconds
Started Apr 15 01:29:42 PM PDT 24
Finished Apr 15 01:29:49 PM PDT 24
Peak memory 216600 kb
Host smart-af309d27-efc7-42e4-baaf-bb5202754e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159482572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3159482572
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1510198951
Short name T399
Test name
Test status
Simulation time 566223980 ps
CPU time 10.33 seconds
Started Apr 15 01:29:50 PM PDT 24
Finished Apr 15 01:30:01 PM PDT 24
Peak memory 216584 kb
Host smart-9d7c1efb-96d5-402f-8ccb-c6fd3d6cbcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510198951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1510198951
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.725883294
Short name T638
Test name
Test status
Simulation time 69802975 ps
CPU time 0.85 seconds
Started Apr 15 01:29:47 PM PDT 24
Finished Apr 15 01:29:48 PM PDT 24
Peak memory 205888 kb
Host smart-52fcc0d0-f995-4124-9227-78efaebcabfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725883294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.725883294
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.544471642
Short name T609
Test name
Test status
Simulation time 4671838849 ps
CPU time 6.04 seconds
Started Apr 15 01:29:53 PM PDT 24
Finished Apr 15 01:29:59 PM PDT 24
Peak memory 216604 kb
Host smart-0ca9c2da-36a9-4c12-9380-2ba0cb7f4ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544471642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.544471642
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1417803470
Short name T518
Test name
Test status
Simulation time 60980677 ps
CPU time 0.68 seconds
Started Apr 15 01:30:09 PM PDT 24
Finished Apr 15 01:30:10 PM PDT 24
Peak memory 205436 kb
Host smart-c4880a99-8a1f-4868-82de-d4196b2c044c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417803470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1417803470
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3721613138
Short name T509
Test name
Test status
Simulation time 43992488 ps
CPU time 0.71 seconds
Started Apr 15 01:29:57 PM PDT 24
Finished Apr 15 01:29:58 PM PDT 24
Peak memory 205632 kb
Host smart-3b1fb28b-5e5f-4e83-ab7c-598cb1b60e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721613138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3721613138
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1570052103
Short name T691
Test name
Test status
Simulation time 6878686788 ps
CPU time 33.87 seconds
Started Apr 15 01:30:03 PM PDT 24
Finished Apr 15 01:30:37 PM PDT 24
Peak memory 249420 kb
Host smart-fa734107-2797-41c1-9d37-63e5e3224b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570052103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1570052103
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2976462637
Short name T219
Test name
Test status
Simulation time 10653634303 ps
CPU time 16.29 seconds
Started Apr 15 01:30:00 PM PDT 24
Finished Apr 15 01:30:17 PM PDT 24
Peak memory 218864 kb
Host smart-9db1219c-f1c4-451e-a93e-1e9a60021762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976462637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2976462637
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3411272555
Short name T49
Test name
Test status
Simulation time 1210360845 ps
CPU time 7.18 seconds
Started Apr 15 01:30:03 PM PDT 24
Finished Apr 15 01:30:10 PM PDT 24
Peak memory 223004 kb
Host smart-c80b95ad-51f7-4960-9347-b0f8e309dd06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3411272555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3411272555
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2218338023
Short name T400
Test name
Test status
Simulation time 828113888 ps
CPU time 14.82 seconds
Started Apr 15 01:29:55 PM PDT 24
Finished Apr 15 01:30:10 PM PDT 24
Peak memory 216532 kb
Host smart-854fc2cd-b589-415d-ab0d-9b27ca92291f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218338023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2218338023
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3035514100
Short name T664
Test name
Test status
Simulation time 8617546201 ps
CPU time 7.99 seconds
Started Apr 15 01:29:56 PM PDT 24
Finished Apr 15 01:30:04 PM PDT 24
Peak memory 216548 kb
Host smart-e01f6d7d-6181-46d9-992e-bd8f9ccbcca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035514100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3035514100
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.474018020
Short name T586
Test name
Test status
Simulation time 379293483 ps
CPU time 5.51 seconds
Started Apr 15 01:30:00 PM PDT 24
Finished Apr 15 01:30:06 PM PDT 24
Peak memory 216600 kb
Host smart-0a264cb8-19c0-4985-bdf5-79ae1b0d8649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474018020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.474018020
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1049209863
Short name T23
Test name
Test status
Simulation time 24725373 ps
CPU time 0.67 seconds
Started Apr 15 01:29:55 PM PDT 24
Finished Apr 15 01:29:56 PM PDT 24
Peak memory 205868 kb
Host smart-56b85226-3dd7-493d-9eea-96e25c7d8f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049209863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1049209863
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2563938807
Short name T271
Test name
Test status
Simulation time 1845467079 ps
CPU time 4.62 seconds
Started Apr 15 01:30:00 PM PDT 24
Finished Apr 15 01:30:05 PM PDT 24
Peak memory 219348 kb
Host smart-4ef70627-389a-4e92-b4ca-268af89a767d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563938807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2563938807
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1482489768
Short name T663
Test name
Test status
Simulation time 52632263 ps
CPU time 0.7 seconds
Started Apr 15 01:30:30 PM PDT 24
Finished Apr 15 01:30:31 PM PDT 24
Peak memory 205300 kb
Host smart-61f0614a-3750-4d07-834e-6369343a3100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482489768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1482489768
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.498386319
Short name T494
Test name
Test status
Simulation time 37856136 ps
CPU time 0.73 seconds
Started Apr 15 01:30:09 PM PDT 24
Finished Apr 15 01:30:11 PM PDT 24
Peak memory 206608 kb
Host smart-7812e2fa-97d9-4786-950e-eef4c177de15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498386319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.498386319
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1942989959
Short name T297
Test name
Test status
Simulation time 14074831020 ps
CPU time 41.15 seconds
Started Apr 15 01:30:20 PM PDT 24
Finished Apr 15 01:31:02 PM PDT 24
Peak memory 249352 kb
Host smart-d7803beb-f907-44a6-be74-6d5e43f6ebcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942989959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1942989959
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1592095224
Short name T166
Test name
Test status
Simulation time 900393978 ps
CPU time 9.85 seconds
Started Apr 15 01:30:15 PM PDT 24
Finished Apr 15 01:30:26 PM PDT 24
Peak memory 222752 kb
Host smart-1985354b-23a9-4829-af25-48bcfebfa7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592095224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1592095224
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1467832455
Short name T280
Test name
Test status
Simulation time 931847616 ps
CPU time 17.97 seconds
Started Apr 15 01:30:18 PM PDT 24
Finished Apr 15 01:30:37 PM PDT 24
Peak memory 240092 kb
Host smart-6acee81e-c647-4996-a111-a034344a7f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467832455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1467832455
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1936172017
Short name T668
Test name
Test status
Simulation time 728705143 ps
CPU time 10.52 seconds
Started Apr 15 01:30:14 PM PDT 24
Finished Apr 15 01:30:26 PM PDT 24
Peak memory 236348 kb
Host smart-7a162e27-3fc1-4311-b206-70468f7be344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936172017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1936172017
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3438283784
Short name T675
Test name
Test status
Simulation time 1114989888 ps
CPU time 16.74 seconds
Started Apr 15 01:30:26 PM PDT 24
Finished Apr 15 01:30:43 PM PDT 24
Peak memory 219780 kb
Host smart-81b37c5a-7dd5-469a-bf42-c6f74a22e60b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3438283784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3438283784
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.428895094
Short name T464
Test name
Test status
Simulation time 4773863277 ps
CPU time 16.59 seconds
Started Apr 15 01:30:14 PM PDT 24
Finished Apr 15 01:30:31 PM PDT 24
Peak memory 216516 kb
Host smart-b7b473fd-a974-4562-9fb9-b2206c8481ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428895094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.428895094
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1605267246
Short name T690
Test name
Test status
Simulation time 10168084641 ps
CPU time 6.57 seconds
Started Apr 15 01:30:10 PM PDT 24
Finished Apr 15 01:30:17 PM PDT 24
Peak memory 216600 kb
Host smart-bab42170-df01-42b0-a848-1750f889cb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605267246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1605267246
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3421918813
Short name T59
Test name
Test status
Simulation time 885937011 ps
CPU time 3.18 seconds
Started Apr 15 01:30:14 PM PDT 24
Finished Apr 15 01:30:18 PM PDT 24
Peak memory 216604 kb
Host smart-cfa34f86-ca1b-45fb-96ae-f9183a93c519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421918813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3421918813
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.664891668
Short name T442
Test name
Test status
Simulation time 106593905 ps
CPU time 0.95 seconds
Started Apr 15 01:30:14 PM PDT 24
Finished Apr 15 01:30:16 PM PDT 24
Peak memory 206896 kb
Host smart-c534a722-d761-4f6a-9e12-a0f9804fd4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664891668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.664891668
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2743083910
Short name T546
Test name
Test status
Simulation time 30268465 ps
CPU time 0.68 seconds
Started Apr 15 01:31:05 PM PDT 24
Finished Apr 15 01:31:06 PM PDT 24
Peak memory 204832 kb
Host smart-eb9d4d48-8b97-4a20-aa6e-e0287437b28c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743083910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2743083910
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2171732400
Short name T709
Test name
Test status
Simulation time 15412731 ps
CPU time 0.77 seconds
Started Apr 15 01:30:28 PM PDT 24
Finished Apr 15 01:30:29 PM PDT 24
Peak memory 206632 kb
Host smart-8c92e648-2826-40fa-bccf-2a097a0a5c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171732400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2171732400
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.928633943
Short name T711
Test name
Test status
Simulation time 26360466900 ps
CPU time 88.15 seconds
Started Apr 15 01:30:40 PM PDT 24
Finished Apr 15 01:32:09 PM PDT 24
Peak memory 250600 kb
Host smart-87aea315-c7bd-47a3-ae59-ec0d1b2b8c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928633943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.928633943
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2815905295
Short name T116
Test name
Test status
Simulation time 3786303919 ps
CPU time 18.7 seconds
Started Apr 15 01:30:35 PM PDT 24
Finished Apr 15 01:30:54 PM PDT 24
Peak memory 218304 kb
Host smart-c86fa4ec-be16-444c-8369-f7088f5a9353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815905295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2815905295
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1891214434
Short name T161
Test name
Test status
Simulation time 76905867953 ps
CPU time 128.4 seconds
Started Apr 15 01:30:38 PM PDT 24
Finished Apr 15 01:32:47 PM PDT 24
Peak memory 250784 kb
Host smart-dfefbbea-05f2-4b76-9601-317c4eaacd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891214434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1891214434
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1380464870
Short name T311
Test name
Test status
Simulation time 3970317988 ps
CPU time 14.3 seconds
Started Apr 15 01:30:31 PM PDT 24
Finished Apr 15 01:30:46 PM PDT 24
Peak memory 234788 kb
Host smart-d2578100-86f8-405d-a466-b90d8fa3391e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380464870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1380464870
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.4089337318
Short name T681
Test name
Test status
Simulation time 1215435917 ps
CPU time 3.54 seconds
Started Apr 15 01:30:39 PM PDT 24
Finished Apr 15 01:30:43 PM PDT 24
Peak memory 220748 kb
Host smart-bda03439-1c4a-441e-b76d-860dba2a2963
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4089337318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.4089337318
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.699924714
Short name T347
Test name
Test status
Simulation time 158141286 ps
CPU time 1.02 seconds
Started Apr 15 01:30:48 PM PDT 24
Finished Apr 15 01:30:49 PM PDT 24
Peak memory 206888 kb
Host smart-0b9455c0-b970-48c1-bf8a-35a1446356a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699924714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.699924714
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.480368094
Short name T16
Test name
Test status
Simulation time 3426106409 ps
CPU time 37.49 seconds
Started Apr 15 01:30:32 PM PDT 24
Finished Apr 15 01:31:09 PM PDT 24
Peak memory 216600 kb
Host smart-e56b6ae2-521d-4e1c-a5df-f0759271d5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480368094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.480368094
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1791243772
Short name T502
Test name
Test status
Simulation time 331467529 ps
CPU time 3.27 seconds
Started Apr 15 01:30:26 PM PDT 24
Finished Apr 15 01:30:30 PM PDT 24
Peak memory 216504 kb
Host smart-6f20e9f8-d93e-4716-a887-66d367f338c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791243772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1791243772
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3590056384
Short name T702
Test name
Test status
Simulation time 229101045 ps
CPU time 3.5 seconds
Started Apr 15 01:30:32 PM PDT 24
Finished Apr 15 01:30:36 PM PDT 24
Peak memory 216556 kb
Host smart-8544acef-a575-4637-818a-cdd0f016ef72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590056384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3590056384
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4248178448
Short name T56
Test name
Test status
Simulation time 49676317 ps
CPU time 0.82 seconds
Started Apr 15 01:30:55 PM PDT 24
Finished Apr 15 01:30:56 PM PDT 24
Peak memory 205880 kb
Host smart-0b1f4d49-b341-4e2b-b10c-68ffa4c0033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248178448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4248178448
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2202073406
Short name T310
Test name
Test status
Simulation time 20791409978 ps
CPU time 15.15 seconds
Started Apr 15 01:30:35 PM PDT 24
Finished Apr 15 01:30:50 PM PDT 24
Peak memory 235160 kb
Host smart-2403fe45-de4b-40c5-96d5-868500eb442e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202073406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2202073406
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.912982673
Short name T593
Test name
Test status
Simulation time 38397485 ps
CPU time 0.73 seconds
Started Apr 15 01:31:01 PM PDT 24
Finished Apr 15 01:31:02 PM PDT 24
Peak memory 205352 kb
Host smart-62511a68-23f2-4464-99e5-39ebe9775cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912982673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.912982673
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2617339597
Short name T512
Test name
Test status
Simulation time 26362415 ps
CPU time 0.75 seconds
Started Apr 15 01:30:48 PM PDT 24
Finished Apr 15 01:30:49 PM PDT 24
Peak memory 205636 kb
Host smart-652f8ab2-445c-4d58-a2cd-5d3511455673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617339597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2617339597
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2771289132
Short name T181
Test name
Test status
Simulation time 306667886 ps
CPU time 5.29 seconds
Started Apr 15 01:30:49 PM PDT 24
Finished Apr 15 01:30:55 PM PDT 24
Peak memory 222940 kb
Host smart-fb91d08c-f017-423c-b8df-f8efe8b61d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771289132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2771289132
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3324811763
Short name T167
Test name
Test status
Simulation time 2504475040 ps
CPU time 3.88 seconds
Started Apr 15 01:30:48 PM PDT 24
Finished Apr 15 01:30:52 PM PDT 24
Peak memory 219424 kb
Host smart-f2bcc07d-22b8-4242-ad95-3f12798b0946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324811763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3324811763
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2742209983
Short name T196
Test name
Test status
Simulation time 6639021356 ps
CPU time 6.86 seconds
Started Apr 15 01:30:49 PM PDT 24
Finished Apr 15 01:30:56 PM PDT 24
Peak memory 221268 kb
Host smart-254df78f-e5c5-403b-b969-25da51e1553c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742209983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2742209983
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1727423488
Short name T98
Test name
Test status
Simulation time 813552476 ps
CPU time 8.94 seconds
Started Apr 15 01:30:56 PM PDT 24
Finished Apr 15 01:31:06 PM PDT 24
Peak memory 220600 kb
Host smart-7fd33978-fe63-43a8-8969-3d3b9b4005e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1727423488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1727423488
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1863041028
Short name T499
Test name
Test status
Simulation time 16651377506 ps
CPU time 14.53 seconds
Started Apr 15 01:30:51 PM PDT 24
Finished Apr 15 01:31:06 PM PDT 24
Peak memory 216592 kb
Host smart-27101d12-67e4-4206-a123-a63351d989ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863041028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1863041028
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.646261294
Short name T635
Test name
Test status
Simulation time 147267555 ps
CPU time 1.63 seconds
Started Apr 15 01:30:43 PM PDT 24
Finished Apr 15 01:30:45 PM PDT 24
Peak memory 216572 kb
Host smart-9a0696b1-c37d-4e66-8cb4-78e6a7b7a52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646261294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.646261294
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3568827729
Short name T498
Test name
Test status
Simulation time 228913698 ps
CPU time 0.89 seconds
Started Apr 15 01:30:44 PM PDT 24
Finished Apr 15 01:30:45 PM PDT 24
Peak memory 206860 kb
Host smart-f70c9c2b-e6ae-4c3f-861a-9eb56d0fe49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568827729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3568827729
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3486929571
Short name T299
Test name
Test status
Simulation time 113489024 ps
CPU time 2.65 seconds
Started Apr 15 01:30:48 PM PDT 24
Finished Apr 15 01:30:51 PM PDT 24
Peak memory 222224 kb
Host smart-22990c3b-fb29-46d2-87ce-c76f6566fa29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486929571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3486929571
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.871420620
Short name T578
Test name
Test status
Simulation time 127528845 ps
CPU time 0.7 seconds
Started Apr 15 01:31:36 PM PDT 24
Finished Apr 15 01:31:37 PM PDT 24
Peak memory 205404 kb
Host smart-9f6edd82-3075-4ec9-acc3-8a4c5a3f249c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871420620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.871420620
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.92361273
Short name T321
Test name
Test status
Simulation time 332539348 ps
CPU time 2.98 seconds
Started Apr 15 01:31:11 PM PDT 24
Finished Apr 15 01:31:14 PM PDT 24
Peak memory 217116 kb
Host smart-c141faf9-c431-42ac-9771-63f3f7844147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92361273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.92361273
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1967121449
Short name T655
Test name
Test status
Simulation time 16480541 ps
CPU time 0.74 seconds
Started Apr 15 01:31:04 PM PDT 24
Finished Apr 15 01:31:05 PM PDT 24
Peak memory 205640 kb
Host smart-1ff32165-72c8-4aa3-bf96-5b7a85bd78e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967121449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1967121449
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3541901288
Short name T364
Test name
Test status
Simulation time 3990653751 ps
CPU time 21.92 seconds
Started Apr 15 01:31:12 PM PDT 24
Finished Apr 15 01:31:34 PM PDT 24
Peak memory 249432 kb
Host smart-349dd89f-91f6-4dc0-96f1-bd7fa895b8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541901288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3541901288
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.4231295946
Short name T164
Test name
Test status
Simulation time 14670151043 ps
CPU time 38.96 seconds
Started Apr 15 01:31:06 PM PDT 24
Finished Apr 15 01:31:45 PM PDT 24
Peak memory 223904 kb
Host smart-6b7100a0-9815-490e-b15f-a48b308497f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231295946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.4231295946
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.782412755
Short name T329
Test name
Test status
Simulation time 13565195968 ps
CPU time 20.88 seconds
Started Apr 15 01:31:07 PM PDT 24
Finished Apr 15 01:31:28 PM PDT 24
Peak memory 239252 kb
Host smart-fe8230dc-3bb6-4b76-b168-2170f3abc447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782412755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.782412755
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4083360199
Short name T10
Test name
Test status
Simulation time 161302330 ps
CPU time 4.17 seconds
Started Apr 15 01:31:16 PM PDT 24
Finished Apr 15 01:31:21 PM PDT 24
Peak memory 222988 kb
Host smart-7ba02c66-fa09-45a0-ad78-5b7fa1a41bbf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4083360199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4083360199
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2942987430
Short name T432
Test name
Test status
Simulation time 140174228 ps
CPU time 0.92 seconds
Started Apr 15 01:31:20 PM PDT 24
Finished Apr 15 01:31:21 PM PDT 24
Peak memory 206960 kb
Host smart-65d2f724-30cd-4126-a6cf-f8963fd837fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942987430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2942987430
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.163456880
Short name T511
Test name
Test status
Simulation time 2102228649 ps
CPU time 9.44 seconds
Started Apr 15 01:31:04 PM PDT 24
Finished Apr 15 01:31:13 PM PDT 24
Peak memory 216508 kb
Host smart-d3334a9b-2769-418f-8b28-785a846abbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163456880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.163456880
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.342689436
Short name T643
Test name
Test status
Simulation time 34489183 ps
CPU time 1.07 seconds
Started Apr 15 01:31:05 PM PDT 24
Finished Apr 15 01:31:06 PM PDT 24
Peak memory 207976 kb
Host smart-2d0a8217-50aa-4c6d-8db1-400ca6910174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342689436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.342689436
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3435961160
Short name T695
Test name
Test status
Simulation time 106086968 ps
CPU time 0.75 seconds
Started Apr 15 01:31:16 PM PDT 24
Finished Apr 15 01:31:17 PM PDT 24
Peak memory 205856 kb
Host smart-25d758e7-3d72-4f31-8e24-0f43893daa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435961160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3435961160
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3008895626
Short name T594
Test name
Test status
Simulation time 800727581 ps
CPU time 3.3 seconds
Started Apr 15 01:31:12 PM PDT 24
Finished Apr 15 01:31:16 PM PDT 24
Peak memory 224628 kb
Host smart-fbc89128-ca6c-43cb-bb89-ac08f5b4098d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008895626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3008895626
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3993573992
Short name T29
Test name
Test status
Simulation time 16880218 ps
CPU time 0.75 seconds
Started Apr 15 01:23:06 PM PDT 24
Finished Apr 15 01:23:08 PM PDT 24
Peak memory 205388 kb
Host smart-8929ca0e-cf98-4011-8e8a-a07a354e2342
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993573992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
993573992
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1269677552
Short name T607
Test name
Test status
Simulation time 46288042 ps
CPU time 0.77 seconds
Started Apr 15 01:22:57 PM PDT 24
Finished Apr 15 01:22:58 PM PDT 24
Peak memory 206912 kb
Host smart-192a3ca0-33d3-487d-94a4-da4190808463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269677552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1269677552
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2052038978
Short name T367
Test name
Test status
Simulation time 37380186103 ps
CPU time 116.91 seconds
Started Apr 15 01:23:00 PM PDT 24
Finished Apr 15 01:24:57 PM PDT 24
Peak memory 249452 kb
Host smart-0e698bbd-cdf6-4c15-9c92-d4d7e21f17a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052038978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2052038978
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3602455802
Short name T727
Test name
Test status
Simulation time 164173504 ps
CPU time 4.97 seconds
Started Apr 15 01:22:59 PM PDT 24
Finished Apr 15 01:23:05 PM PDT 24
Peak memory 223872 kb
Host smart-5380aed3-c40a-48b0-a45c-be434ed4059b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602455802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3602455802
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3440424131
Short name T235
Test name
Test status
Simulation time 1073273723 ps
CPU time 11.72 seconds
Started Apr 15 01:22:59 PM PDT 24
Finished Apr 15 01:23:11 PM PDT 24
Peak memory 222332 kb
Host smart-4fd06bd7-ecc9-4211-b4b8-712d4e10a7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440424131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3440424131
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2490075493
Short name T31
Test name
Test status
Simulation time 109924315 ps
CPU time 1.03 seconds
Started Apr 15 01:22:55 PM PDT 24
Finished Apr 15 01:22:56 PM PDT 24
Peak memory 216976 kb
Host smart-c3e2d72e-06d1-42c6-9bcc-a2e9781ac777
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490075493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2490075493
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1153889186
Short name T72
Test name
Test status
Simulation time 18902038740 ps
CPU time 24.39 seconds
Started Apr 15 01:23:00 PM PDT 24
Finished Apr 15 01:23:25 PM PDT 24
Peak memory 224516 kb
Host smart-252162ca-b87c-4191-91dd-7277416f22ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153889186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1153889186
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1424837505
Short name T301
Test name
Test status
Simulation time 12280313380 ps
CPU time 4.68 seconds
Started Apr 15 01:22:55 PM PDT 24
Finished Apr 15 01:23:00 PM PDT 24
Peak memory 223300 kb
Host smart-aa25ea15-cc11-4579-bcf5-ad3a0874525a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424837505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1424837505
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.576561875
Short name T6
Test name
Test status
Simulation time 1350115775 ps
CPU time 4.83 seconds
Started Apr 15 01:23:05 PM PDT 24
Finished Apr 15 01:23:10 PM PDT 24
Peak memory 218876 kb
Host smart-0392108e-f31f-4044-a8e5-38994d893633
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=576561875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.576561875
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4039475434
Short name T345
Test name
Test status
Simulation time 45181414 ps
CPU time 0.98 seconds
Started Apr 15 01:23:04 PM PDT 24
Finished Apr 15 01:23:05 PM PDT 24
Peak memory 206836 kb
Host smart-57f6e07c-897b-440f-b291-ff1fe61dbe1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039475434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4039475434
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2636370167
Short name T387
Test name
Test status
Simulation time 19384461685 ps
CPU time 56.28 seconds
Started Apr 15 01:22:57 PM PDT 24
Finished Apr 15 01:23:54 PM PDT 24
Peak memory 216580 kb
Host smart-cff8b223-c086-4027-8add-906907048dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636370167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2636370167
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.886144936
Short name T121
Test name
Test status
Simulation time 1762114337 ps
CPU time 5.64 seconds
Started Apr 15 01:22:55 PM PDT 24
Finished Apr 15 01:23:01 PM PDT 24
Peak memory 216524 kb
Host smart-be3d610f-fc6e-457d-ac95-7aa829d95e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886144936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.886144936
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.4002105722
Short name T706
Test name
Test status
Simulation time 365329202 ps
CPU time 10.22 seconds
Started Apr 15 01:22:56 PM PDT 24
Finished Apr 15 01:23:06 PM PDT 24
Peak memory 216596 kb
Host smart-e5b950ce-e257-4060-9faf-eeb2ecbae452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002105722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.4002105722
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3231954780
Short name T657
Test name
Test status
Simulation time 140120564 ps
CPU time 1 seconds
Started Apr 15 01:22:57 PM PDT 24
Finished Apr 15 01:22:59 PM PDT 24
Peak memory 206900 kb
Host smart-68110e76-16d3-4d9d-9082-8423800d2652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231954780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3231954780
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1318399374
Short name T418
Test name
Test status
Simulation time 21638997 ps
CPU time 0.7 seconds
Started Apr 15 01:23:13 PM PDT 24
Finished Apr 15 01:23:14 PM PDT 24
Peak memory 205356 kb
Host smart-46e8bb07-003c-4cc7-a54a-670882dbc79c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318399374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
318399374
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2490667835
Short name T178
Test name
Test status
Simulation time 6881844312 ps
CPU time 32.66 seconds
Started Apr 15 01:23:11 PM PDT 24
Finished Apr 15 01:23:44 PM PDT 24
Peak memory 233032 kb
Host smart-73e2b3d8-9249-4bab-8b6a-eb4db2e1af1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490667835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2490667835
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2851102788
Short name T592
Test name
Test status
Simulation time 58721381 ps
CPU time 0.86 seconds
Started Apr 15 01:23:03 PM PDT 24
Finished Apr 15 01:23:04 PM PDT 24
Peak memory 206644 kb
Host smart-c5d4c7a6-c8af-40dd-98d8-c42dfff08ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851102788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2851102788
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1690535148
Short name T287
Test name
Test status
Simulation time 593170075 ps
CPU time 19.53 seconds
Started Apr 15 01:23:08 PM PDT 24
Finished Apr 15 01:23:28 PM PDT 24
Peak memory 248896 kb
Host smart-4d9b112b-325d-44f9-9830-9a6348534489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690535148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1690535148
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1091741950
Short name T37
Test name
Test status
Simulation time 3730544507 ps
CPU time 4.2 seconds
Started Apr 15 01:23:07 PM PDT 24
Finished Apr 15 01:23:12 PM PDT 24
Peak memory 219432 kb
Host smart-70371ba6-6554-4c74-a2f5-ad09dd76e944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091741950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1091741950
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.489342689
Short name T437
Test name
Test status
Simulation time 117434711 ps
CPU time 1.08 seconds
Started Apr 15 01:23:03 PM PDT 24
Finished Apr 15 01:23:05 PM PDT 24
Peak memory 216988 kb
Host smart-8d4ac0df-4ea9-4e2e-901a-730d58e29df6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489342689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.489342689
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.372202712
Short name T202
Test name
Test status
Simulation time 3538083542 ps
CPU time 11.36 seconds
Started Apr 15 01:23:07 PM PDT 24
Finished Apr 15 01:23:18 PM PDT 24
Peak memory 223204 kb
Host smart-0df4bd0a-b712-4332-98e2-469ef8ed851e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372202712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.372202712
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.49966173
Short name T508
Test name
Test status
Simulation time 989610317 ps
CPU time 5.26 seconds
Started Apr 15 01:23:08 PM PDT 24
Finished Apr 15 01:23:13 PM PDT 24
Peak memory 220588 kb
Host smart-5fdc0ccb-7c1b-4aba-810d-e2d01b31c4c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=49966173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct
.49966173
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2596431941
Short name T381
Test name
Test status
Simulation time 1073544394 ps
CPU time 3.91 seconds
Started Apr 15 01:23:08 PM PDT 24
Finished Apr 15 01:23:12 PM PDT 24
Peak memory 216744 kb
Host smart-c4e471ef-d583-4220-a414-6b13d04904c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596431941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2596431941
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4120693270
Short name T503
Test name
Test status
Simulation time 1722640923 ps
CPU time 10.64 seconds
Started Apr 15 01:23:04 PM PDT 24
Finished Apr 15 01:23:16 PM PDT 24
Peak memory 216576 kb
Host smart-42083fc4-91fc-45ad-b232-e23118c224d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120693270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4120693270
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2740809708
Short name T631
Test name
Test status
Simulation time 305825690 ps
CPU time 3.81 seconds
Started Apr 15 01:23:05 PM PDT 24
Finished Apr 15 01:23:09 PM PDT 24
Peak memory 216512 kb
Host smart-d756cba5-9b12-4778-a78a-80a8381830a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740809708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2740809708
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3585474770
Short name T561
Test name
Test status
Simulation time 78051843 ps
CPU time 0.79 seconds
Started Apr 15 01:23:03 PM PDT 24
Finished Apr 15 01:23:05 PM PDT 24
Peak memory 205856 kb
Host smart-21773129-1956-4c91-9e24-c1ffa2305c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585474770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3585474770
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.976158846
Short name T632
Test name
Test status
Simulation time 25004340 ps
CPU time 0.73 seconds
Started Apr 15 01:23:20 PM PDT 24
Finished Apr 15 01:23:21 PM PDT 24
Peak memory 205796 kb
Host smart-ddaa12ac-1bae-4fb4-8feb-8cd6fcbea8b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976158846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.976158846
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1748022368
Short name T199
Test name
Test status
Simulation time 1902108623 ps
CPU time 8.99 seconds
Started Apr 15 01:23:16 PM PDT 24
Finished Apr 15 01:23:25 PM PDT 24
Peak memory 223868 kb
Host smart-08a8fdee-e971-4a1e-9c21-ceb110afca3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748022368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1748022368
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3249574278
Short name T640
Test name
Test status
Simulation time 62272411 ps
CPU time 0.76 seconds
Started Apr 15 01:23:12 PM PDT 24
Finished Apr 15 01:23:14 PM PDT 24
Peak memory 207000 kb
Host smart-aa2da5c3-953d-4c04-994c-9c6e5624162d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249574278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3249574278
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2907427779
Short name T282
Test name
Test status
Simulation time 2977622700 ps
CPU time 46.63 seconds
Started Apr 15 01:23:16 PM PDT 24
Finished Apr 15 01:24:02 PM PDT 24
Peak memory 240708 kb
Host smart-b1c479ab-7d8c-4ec0-812f-2d834f12b225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907427779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2907427779
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.856752471
Short name T680
Test name
Test status
Simulation time 3639770829 ps
CPU time 11.02 seconds
Started Apr 15 01:23:19 PM PDT 24
Finished Apr 15 01:23:30 PM PDT 24
Peak memory 224140 kb
Host smart-5d44556e-bd9e-4022-905e-f64a034be757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856752471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.856752471
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2529633047
Short name T667
Test name
Test status
Simulation time 129353593 ps
CPU time 1.01 seconds
Started Apr 15 01:23:13 PM PDT 24
Finished Apr 15 01:23:14 PM PDT 24
Peak memory 218212 kb
Host smart-e96df2df-7cfd-457e-bc2b-dc2043bc9c85
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529633047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2529633047
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2720519164
Short name T303
Test name
Test status
Simulation time 3441329800 ps
CPU time 10.76 seconds
Started Apr 15 01:23:12 PM PDT 24
Finished Apr 15 01:23:23 PM PDT 24
Peak memory 223424 kb
Host smart-a140833d-8cad-42ce-9866-e4f29fbe5fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720519164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2720519164
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4064272339
Short name T692
Test name
Test status
Simulation time 19812663867 ps
CPU time 16.95 seconds
Started Apr 15 01:23:13 PM PDT 24
Finished Apr 15 01:23:31 PM PDT 24
Peak memory 223112 kb
Host smart-1e8331fd-b25d-45a8-840e-304b8bdfa9cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4064272339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4064272339
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3734838098
Short name T486
Test name
Test status
Simulation time 95169941 ps
CPU time 1.06 seconds
Started Apr 15 01:23:20 PM PDT 24
Finished Apr 15 01:23:21 PM PDT 24
Peak memory 206888 kb
Host smart-35824677-ebf4-42ff-9114-262a7000dd90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734838098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3734838098
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2538711281
Short name T384
Test name
Test status
Simulation time 12249333312 ps
CPU time 51.16 seconds
Started Apr 15 01:23:14 PM PDT 24
Finished Apr 15 01:24:05 PM PDT 24
Peak memory 216484 kb
Host smart-4bc51e96-854a-48f6-b6c9-a0b30fb06e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538711281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2538711281
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2614204121
Short name T566
Test name
Test status
Simulation time 7715231978 ps
CPU time 22.84 seconds
Started Apr 15 01:23:13 PM PDT 24
Finished Apr 15 01:23:37 PM PDT 24
Peak memory 216552 kb
Host smart-3bbd7456-c4ce-4449-a6f2-862150c57acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614204121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2614204121
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3069243935
Short name T504
Test name
Test status
Simulation time 184612584 ps
CPU time 1.9 seconds
Started Apr 15 01:23:13 PM PDT 24
Finished Apr 15 01:23:15 PM PDT 24
Peak memory 216616 kb
Host smart-dc0452cf-365c-4a96-9c51-4c964b805842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069243935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3069243935
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4233187317
Short name T604
Test name
Test status
Simulation time 149640302 ps
CPU time 0.83 seconds
Started Apr 15 01:23:15 PM PDT 24
Finished Apr 15 01:23:16 PM PDT 24
Peak memory 205872 kb
Host smart-ae890baa-5d0d-40ff-b063-79707a6cae69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233187317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4233187317
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3193673338
Short name T575
Test name
Test status
Simulation time 53172821 ps
CPU time 0.72 seconds
Started Apr 15 01:23:28 PM PDT 24
Finished Apr 15 01:23:29 PM PDT 24
Peak memory 205572 kb
Host smart-81526634-fd7e-4cd9-8142-c6e66375fa6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193673338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
193673338
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3343090457
Short name T51
Test name
Test status
Simulation time 696491456 ps
CPU time 4.67 seconds
Started Apr 15 01:23:24 PM PDT 24
Finished Apr 15 01:23:29 PM PDT 24
Peak memory 224124 kb
Host smart-56ac8467-c68c-432a-817d-656bee621012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343090457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3343090457
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.4164600693
Short name T473
Test name
Test status
Simulation time 17365258 ps
CPU time 0.78 seconds
Started Apr 15 01:23:20 PM PDT 24
Finished Apr 15 01:23:21 PM PDT 24
Peak memory 205600 kb
Host smart-3d49748f-c46e-42e5-85de-141f014c9447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164600693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.4164600693
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1821260365
Short name T87
Test name
Test status
Simulation time 2427217977 ps
CPU time 8.39 seconds
Started Apr 15 01:23:24 PM PDT 24
Finished Apr 15 01:23:33 PM PDT 24
Peak memory 241224 kb
Host smart-433c5d72-701c-43c5-8cf6-899b7165d854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821260365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1821260365
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2236019525
Short name T696
Test name
Test status
Simulation time 934512757 ps
CPU time 5.83 seconds
Started Apr 15 01:23:24 PM PDT 24
Finished Apr 15 01:23:31 PM PDT 24
Peak memory 216904 kb
Host smart-7e4ff693-5bea-4ee4-b79b-1e629e65d8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236019525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2236019525
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1330194731
Short name T163
Test name
Test status
Simulation time 691019882 ps
CPU time 6.5 seconds
Started Apr 15 01:23:22 PM PDT 24
Finished Apr 15 01:23:29 PM PDT 24
Peak memory 222152 kb
Host smart-49f23a7e-b6c4-402b-9124-0aff0e915181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330194731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1330194731
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3679802764
Short name T526
Test name
Test status
Simulation time 142278364 ps
CPU time 1.03 seconds
Started Apr 15 01:23:20 PM PDT 24
Finished Apr 15 01:23:21 PM PDT 24
Peak memory 216964 kb
Host smart-8f012c52-d407-4945-98c1-7ad1f0606b0e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679802764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3679802764
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3640940770
Short name T704
Test name
Test status
Simulation time 382153067 ps
CPU time 8.23 seconds
Started Apr 15 01:23:20 PM PDT 24
Finished Apr 15 01:23:29 PM PDT 24
Peak memory 222884 kb
Host smart-e21a170a-1bae-416a-a978-2ff4883cdfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640940770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3640940770
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.571785239
Short name T513
Test name
Test status
Simulation time 116013117 ps
CPU time 3.51 seconds
Started Apr 15 01:23:31 PM PDT 24
Finished Apr 15 01:23:35 PM PDT 24
Peak memory 220772 kb
Host smart-3cbb9958-3da3-4fbe-8781-85d368376a8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=571785239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.571785239
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2335522340
Short name T633
Test name
Test status
Simulation time 1352087089 ps
CPU time 8.68 seconds
Started Apr 15 01:23:18 PM PDT 24
Finished Apr 15 01:23:28 PM PDT 24
Peak memory 216456 kb
Host smart-1d223086-bc1b-4069-b683-08754ae92e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335522340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2335522340
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1429690963
Short name T490
Test name
Test status
Simulation time 38916122 ps
CPU time 1.06 seconds
Started Apr 15 01:23:19 PM PDT 24
Finished Apr 15 01:23:20 PM PDT 24
Peak memory 207160 kb
Host smart-b0c89e4b-52ab-4a43-8616-639a934a548f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429690963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1429690963
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2335501198
Short name T614
Test name
Test status
Simulation time 816912541 ps
CPU time 1.21 seconds
Started Apr 15 01:23:20 PM PDT 24
Finished Apr 15 01:23:22 PM PDT 24
Peak memory 206892 kb
Host smart-729de010-d3bb-4fbf-bbc7-0978a0b95608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335501198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2335501198
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3909316639
Short name T652
Test name
Test status
Simulation time 13390895 ps
CPU time 0.73 seconds
Started Apr 15 01:23:31 PM PDT 24
Finished Apr 15 01:23:32 PM PDT 24
Peak memory 205432 kb
Host smart-6053bfbd-c425-41f2-9ba4-337bdfd7b5bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909316639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
909316639
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.4237484164
Short name T637
Test name
Test status
Simulation time 16319905 ps
CPU time 0.76 seconds
Started Apr 15 01:23:28 PM PDT 24
Finished Apr 15 01:23:29 PM PDT 24
Peak memory 205632 kb
Host smart-6617e579-e6e1-4104-9b9a-7b3ae70ce1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237484164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4237484164
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3475747253
Short name T365
Test name
Test status
Simulation time 352752373 ps
CPU time 10.12 seconds
Started Apr 15 01:23:31 PM PDT 24
Finished Apr 15 01:23:41 PM PDT 24
Peak memory 232960 kb
Host smart-9a8d63a4-ac6c-4192-abe8-1ea2b0df0583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475747253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3475747253
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.949318369
Short name T267
Test name
Test status
Simulation time 1118704453 ps
CPU time 17.73 seconds
Started Apr 15 01:23:33 PM PDT 24
Finished Apr 15 01:23:51 PM PDT 24
Peak memory 236524 kb
Host smart-a71dbeba-72ff-40bf-b554-05c7ac1d2774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949318369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.949318369
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3778133388
Short name T563
Test name
Test status
Simulation time 45329721 ps
CPU time 1.06 seconds
Started Apr 15 01:23:29 PM PDT 24
Finished Apr 15 01:23:31 PM PDT 24
Peak memory 216980 kb
Host smart-6a7c4b5a-81be-44a1-a73c-2204a13745b5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778133388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3778133388
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3193810597
Short name T304
Test name
Test status
Simulation time 230094744 ps
CPU time 3.96 seconds
Started Apr 15 01:23:27 PM PDT 24
Finished Apr 15 01:23:32 PM PDT 24
Peak memory 223044 kb
Host smart-2bac556d-62dc-46fd-9921-4b1d1dc0b161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193810597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3193810597
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1521631025
Short name T50
Test name
Test status
Simulation time 1691863830 ps
CPU time 8.68 seconds
Started Apr 15 01:23:31 PM PDT 24
Finished Apr 15 01:23:40 PM PDT 24
Peak memory 219472 kb
Host smart-46d1b539-3cf7-4e6c-b7cf-b936ada15eae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1521631025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1521631025
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4245687094
Short name T60
Test name
Test status
Simulation time 1884257970 ps
CPU time 13.73 seconds
Started Apr 15 01:23:28 PM PDT 24
Finished Apr 15 01:23:42 PM PDT 24
Peak memory 216536 kb
Host smart-3fd390a3-3d3c-4dc5-a952-4e1ea5626bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245687094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4245687094
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2214098359
Short name T465
Test name
Test status
Simulation time 4088158139 ps
CPU time 7.65 seconds
Started Apr 15 01:23:27 PM PDT 24
Finished Apr 15 01:23:35 PM PDT 24
Peak memory 216592 kb
Host smart-fa2f1ad5-655d-47fb-88e2-fd86b1b1a5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214098359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2214098359
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.4051691362
Short name T694
Test name
Test status
Simulation time 270716870 ps
CPU time 11.52 seconds
Started Apr 15 01:23:27 PM PDT 24
Finished Apr 15 01:23:39 PM PDT 24
Peak memory 216520 kb
Host smart-639962f6-e29b-4052-b7c8-6863a7476ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051691362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.4051691362
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.786807503
Short name T405
Test name
Test status
Simulation time 54290308 ps
CPU time 0.75 seconds
Started Apr 15 01:23:28 PM PDT 24
Finished Apr 15 01:23:29 PM PDT 24
Peak memory 206068 kb
Host smart-617e41b1-3eb3-4231-a522-0d80f4bb34c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786807503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.786807503
Directory /workspace/9.spi_device_tpm_sts_read/latest
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