Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	211919	1			T1	1		T2	21		T4	1
all_values[1]	211919	1			T1	1		T2	21		T4	1
all_values[2]	211919	1			T1	1		T2	21		T4	1
all_values[3]	211919	1			T1	1		T2	21		T4	1
all_values[4]	211919	1			T1	1		T2	21		T4	1
all_values[5]	211919	1			T1	1		T2	21		T4	1
all_values[6]	211919	1			T1	1		T2	21		T4	1
all_values[7]	211919	1			T1	1		T2	21		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1693000

1

T1

8

T2

95

T4

8

auto[1]

2352

1

T2

73

T42

95

T43

144

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1693201

1

T1

8

T2

108

T4

8

auto[1]

2151

1

T2

60

T15

1

T70

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	211524	1			T1	1		T2	6		T4	1
all_values[0]	auto[0]	auto[1]	113	1			T2	5		T42	7		T43	11
all_values[0]	auto[1]	auto[0]	144	1			T2	8		T42	3		T43	5
all_values[0]	auto[1]	auto[1]	138	1			T2	2		T42	4		T43	8
all_values[1]	auto[0]	auto[0]	211517	1			T1	1		T2	12		T4	1
all_values[1]	auto[0]	auto[1]	117	1			T2	3		T42	5		T43	7
all_values[1]	auto[1]	auto[0]	165	1			T2	3		T42	7		T43	16
all_values[1]	auto[1]	auto[1]	120	1			T2	3		T42	6		T43	3
all_values[2]	auto[0]	auto[0]	211523	1			T1	1		T2	8		T4	1
all_values[2]	auto[0]	auto[1]	109	1			T2	2		T42	6		T43	6
all_values[2]	auto[1]	auto[0]	180	1			T2	5		T42	4		T43	10
all_values[2]	auto[1]	auto[1]	107	1			T2	6		T42	7		T43	10
all_values[3]	auto[0]	auto[0]	211493	1			T1	1		T2	4		T4	1
all_values[3]	auto[0]	auto[1]	143	1			T2	5		T70	2		T42	7
all_values[3]	auto[1]	auto[0]	185	1			T2	8		T42	6		T43	17
all_values[3]	auto[1]	auto[1]	98	1			T2	4		T42	7		T43	6
all_values[4]	auto[0]	auto[0]	211480	1			T1	1		T2	9		T4	1
all_values[4]	auto[0]	auto[1]	137	1			T2	2		T295	1		T42	5
all_values[4]	auto[1]	auto[0]	186	1			T2	7		T42	10		T43	13
all_values[4]	auto[1]	auto[1]	116	1			T2	3		T42	5		T43	8
all_values[5]	auto[0]	auto[0]	211255	1			T1	1		T2	5		T4	1
all_values[5]	auto[0]	auto[1]	360	1			T2	7		T15	1		T18	4
all_values[5]	auto[1]	auto[0]	222	1			T2	7		T42	9		T43	6
all_values[5]	auto[1]	auto[1]	82	1			T2	2		T42	6		T43	6
all_values[6]	auto[0]	auto[0]	211498	1			T1	1		T2	5		T4	1
all_values[6]	auto[0]	auto[1]	128	1			T2	6		T42	4		T43	6
all_values[6]	auto[1]	auto[0]	152	1			T2	6		T42	8		T43	6
all_values[6]	auto[1]	auto[1]	141	1			T2	4		T42	5		T43	13
all_values[7]	auto[0]	auto[0]	211496	1			T1	1		T2	11		T4	1
all_values[7]	auto[0]	auto[1]	107	1			T2	5		T42	9		T43	5
all_values[7]	auto[1]	auto[0]	181	1			T2	4		T42	2		T43	13
all_values[7]	auto[1]	auto[1]	135	1			T2	1		T42	6		T43	4