Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
72.13	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	33	51	60.71

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	29	19	39.58	100	1	1	0
cr_modeXdummyXnum_lanes	36	4	32	88.89	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1086	1			T1	8		T4	4		T8	2
auto[SpiFlashAddrCfg]	813	1			T1	12		T10	5		T67	6
auto[SpiFlashAddr3b]	1002	1			T1	12		T4	2		T5	6
auto[SpiFlashAddr4b]	799	1			T1	4		T4	10		T5	12

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2890

1

T1

36

T4

16

T5

18

auto[1]

810

1

T66

14

T57

6

T74

12

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1884

1

T1

8

T4

8

T5

15

auto[1]

1816

1

T1

28

T4

8

T5

3

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1393	1			T1	14		T4	2		T5	3
values[1]	88	1			T4	2		T10	3		T67	2
values[2]	227	1			T66	2		T70	6		T55	6
values[3]	183	1			T1	4		T4	2		T50	10
values[4]	152	1			T9	4		T55	4		T172	4
values[5]	136	1			T1	12		T5	4		T66	2
values[6]	227	1			T1	4		T8	2		T67	4
values[7]	207	1			T5	6		T67	6		T70	5
values[8]	1087	1			T1	2		T4	10		T5	5

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3198

1

T1

36

T4

16

T8

8

auto[1]

502

1

T5

18

T10

8

T70

29

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3588

1

T1

36

T4

16

T5

18

write

112

1

T67

2

T45

4

T73

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1664

1

T1

22

T4

2

T5

10

valids[0x1]

2036

1

T1

14

T4

14

T5

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	134	1			T1	2		T67	4		T55	2
internal_process_ops[0x5a]	204	1			T45	6		T59	4		T79	2
internal_process_ops[0x05]	252	1			T1	2		T45	4		T59	2
internal_process_ops[0x35]	192	1			T4	2		T66	4		T45	2
internal_process_ops[0x15]	184	1			T67	4		T79	4		T174	2
internal_process_ops[0x03]	268	1			T5	5		T50	8		T66	4
internal_process_ops[0x0b]	218	1			T1	2		T4	2		T5	3
internal_process_ops[0x3b]	276	1			T5	4		T9	4		T10	3
internal_process_ops[0x6b]	222	1			T8	2		T70	6		T79	2
internal_process_ops[0xbb]	199	1			T10	5		T66	2		T67	2
internal_process_ops[0xeb]	277	1			T4	2		T5	6		T50	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3650

1

T1

36

T4

16

T5

18

auto[1]

50

1

T73

2

T75

4

T76

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3700

1

T1

36

T4

16

T5

18

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	29	19	39.58	29
Automatically Generated Cross Bins	48	29	19	39.58	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	[auto[SpiFlashAddrDisabled]]	*	[auto[0]]	--	--	2
[auto[1]]	[write]	*	*	*	--	--	16

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddrCfg] , auto[SpiFlashAddr3b] , auto[SpiFlashAddr4b]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

844

1

T1

8

T4

4

T8

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

200

1

T66

6

T74

4

T73

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

396

1

T1

12

T67

6

T55

18

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

216

1

T74

4

T95

4

T193

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

608

1

T1

12

T4

2

T8

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

222

1

T66

4

T57

4

T95

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

478

1

T1

4

T4

10

T8

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

122

1

T66

4

T57

2

T74

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

24

1

T78

2

T236

4

T220

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

18

1

T75

4

T82

2

T83

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

22

1

T45

4

T283

2

T225

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

14

1

T73

2

T76

2

T86

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

6

1

T204

4

T239

2

-

-

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

14

1

T81

4

T187

6

T280

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

10

1

T67

2

T284

2

T285

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

4

1

T81

4

-

-

-

-

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

165

1

T10

5

T70

16

T98

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

152

1

T5

6

T10

3

T70

7

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

185

1

T5

12

T70

6

T159

5

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	4	32	88.89	4

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0] , values[1]]	[valids[0x0]]	--	--	2
[auto[1]]	[values[5]]	[valids[0x1]]	0	1	1

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	234	1			T1	8		T8	2		T79	2
auto[0]	values[0]	valids[0x1]	1124	1			T1	6		T4	2		T66	8
auto[0]	values[1]	valids[0x1]	72	1			T4	2		T67	2		T94	2
auto[0]	values[2]	valids[0x0]	110	1			T66	2		T55	6		T79	2
auto[0]	values[2]	valids[0x1]	72	1			T175	4		T96	6		T179	2
auto[0]	values[3]	valids[0x0]	118	1			T50	10		T28	4		T128	6
auto[0]	values[3]	valids[0x1]	36	1			T1	4		T4	2		T177	2
auto[0]	values[4]	valids[0x0]	72	1			T9	4		T172	4		T177	2
auto[0]	values[4]	valids[0x1]	52	1			T55	4		T115	10		T80	4
auto[0]	values[5]	valids[0x0]	92	1			T1	12		T66	2		T67	2
auto[0]	values[5]	valids[0x1]	22	1			T173	2		T244	2		T122	8
auto[0]	values[6]	valids[0x0]	120	1			T1	2		T8	2		T67	4
auto[0]	values[6]	valids[0x1]	62	1			T1	2		T55	6		T172	6
auto[0]	values[7]	valids[0x0]	88	1			T128	4		T173	4		T73	2
auto[0]	values[7]	valids[0x1]	72	1			T67	6		T48	2		T249	2
auto[0]	values[8]	valids[0x0]	506	1			T4	2		T67	6		T55	2
auto[0]	values[8]	valids[0x1]	346	1			T1	2		T4	8		T8	4
auto[1]	values[0]	valids[0x1]	35	1			T5	3		T159	5		T140	6
auto[1]	values[1]	valids[0x1]	16	1			T10	3		T286	6		T287	5
auto[1]	values[2]	valids[0x0]	32	1			T70	6		T288	4		T289	3
auto[1]	values[2]	valids[0x1]	13	1			T98	5		T290	8		-	-
auto[1]	values[3]	valids[0x0]	22	1			T140	6		T291	2		T292	10
auto[1]	values[3]	valids[0x1]	7	1			T288	3		T293	4		-	-
auto[1]	values[4]	valids[0x0]	25	1			T117	3		T294	4		T289	5
auto[1]	values[4]	valids[0x1]	3	1			T291	3		-	-		-	-
auto[1]	values[5]	valids[0x0]	22	1			T5	4		T98	1		T295	5
auto[1]	values[6]	valids[0x0]	29	1			T70	11		T295	5		T296	3
auto[1]	values[6]	valids[0x1]	16	1			T288	4		T297	5		T290	3
auto[1]	values[7]	valids[0x0]	38	1			T5	6		T70	5		T288	6
auto[1]	values[7]	valids[0x1]	9	1			T298	4		T291	5		-	-
auto[1]	values[8]	valids[0x0]	156	1			T10	5		T98	8		T159	2
auto[1]	values[8]	valids[0x1]	79	1			T5	5		T70	7		T291	6