Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1528246 1 T1 1 T4 1 T5 21544


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1329686 1 T1 1 T4 1 T5 21544
auto[1] 198560 1 T45 1032 T28 1024 T46 612


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 420455 1 T1 1 T4 1 T5 8155
auto[524288:1048575] 124974 1 T5 1177 T9 515 T10 144
auto[1048576:1572863] 143194 1 T5 3069 T6 1174 T10 977
auto[1572864:2097151] 150426 1 T5 1892 T10 3958 T50 513
auto[2097152:2621439] 209020 1 T5 285 T9 19 T10 1714
auto[2621440:3145727] 191500 1 T5 22 T6 7112 T10 3937
auto[3145728:3670015] 142169 1 T5 6914 T10 6768 T50 410
auto[3670016:4194303] 146508 1 T5 30 T9 15 T10 3


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 212316 1 T1 1 T4 1 T5 56
auto[1] 1315930 1 T5 21488 T6 14247 T9 874


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1528246 1 T1 1 T4 1 T5 21544


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 288522 1 T1 1 T4 1 T5 8155
auto[0] auto[0] auto[0:524287] auto[1] 131933 1 T45 1032 T28 1024 T46 612
auto[0] auto[0] auto[524288:1048575] auto[0] 121554 1 T5 1177 T9 515 T10 144
auto[0] auto[0] auto[524288:1048575] auto[1] 3420 1 T168 1 T103 516 T169 1921
auto[0] auto[0] auto[1048576:1572863] auto[0] 131006 1 T5 3069 T6 1174 T10 977
auto[0] auto[0] auto[1048576:1572863] auto[1] 12188 1 T93 257 T48 255 T170 13
auto[0] auto[0] auto[1572864:2097151] auto[0] 136008 1 T5 1892 T10 3958 T50 513
auto[0] auto[0] auto[1572864:2097151] auto[1] 14418 1 T102 3 T170 3882 T103 511
auto[0] auto[0] auto[2097152:2621439] auto[0] 195724 1 T5 285 T9 19 T10 1714
auto[0] auto[0] auto[2097152:2621439] auto[1] 13296 1 T48 530 T102 4 T170 409
auto[0] auto[0] auto[2621440:3145727] auto[0] 177635 1 T5 22 T6 7112 T10 3937
auto[0] auto[0] auto[2621440:3145727] auto[1] 13865 1 T170 1627 T168 2 T103 2176
auto[0] auto[0] auto[3145728:3670015] auto[0] 138125 1 T5 6914 T10 6768 T50 410
auto[0] auto[0] auto[3145728:3670015] auto[1] 4044 1 T103 1 T169 7 T171 1039
auto[0] auto[0] auto[3670016:4194303] auto[0] 141112 1 T5 30 T9 15 T10 3
auto[0] auto[0] auto[3670016:4194303] auto[1] 5396 1 T48 6 T103 515 T169 771


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 212316 1 T1 1 T4 1 T5 56
auto[0] auto[0] auto[1] 1315930 1 T5 21488 T6 14247 T9 874

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