Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
77.40	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	33	95	74.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	33	95	74.22	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2388

1

T1

36

T4

16

T8

8

auto[1]

810

1

T66

14

T57

6

T74

12

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	326	1			T55	32		T174	4		T30	30
values[1]	380	1			T79	20		T29	14		T250	8
values[2]	496	1			T1	36		T4	16		T8	8
values[3]	342	1			T51	6		T57	6		T128	20
values[4]	478	1			T59	26		T173	20		T48	30
values[5]	328	1			T67	30		T211	2		T177	12
values[6]	418	1			T9	4		T66	14		T68	2
values[7]	430	1			T45	26		T127	4		T28	14

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	202	1			T28	14		T128	20		T211	2
values[1]	308	1			T51	6		T59	26		T175	18
values[2]	454	1			T79	20		T127	4		T74	12
values[3]	446	1			T9	4		T50	18		T68	2
values[4]	420	1			T66	14		T46	6		T173	20
values[5]	576	1			T1	36		T4	16		T55	32
values[6]	428	1			T67	30		T299	8		T75	32
values[7]	364	1			T8	8		T57	6		T30	30

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	33	95	74.22	33

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[values[1]]	0	1	1
[auto[0]]	[values[3]]	[values[7]]	0	1	1
[auto[0]]	[values[4]]	[values[6]]	0	1	1
[auto[0]]	[values[7]]	[values[1]]	0	1	1
[auto[1]]	[values[0]]	[values[1] , values[2] , values[3]]	--	--	3
[auto[1]]	[values[0]]	[values[6]]	0	1	1
[auto[1]]	[values[1]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[1]]	[values[7]]	0	1	1
[auto[1]]	[values[2]]	[values[4]]	0	1	1
[auto[1]]	[values[2]]	[values[7]]	0	1	1
[auto[1]]	[values[3]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[3]]	[values[3]]	0	1	1
[auto[1]]	[values[3]]	[values[5]]	0	1	1
[auto[1]]	[values[4]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[4]]	[values[5]]	0	1	1
[auto[1]]	[values[4]]	[values[7]]	0	1	1
[auto[1]]	[values[5]]	[values[1] , values[2] , values[3] , values[4]]	--	--	4
[auto[1]]	[values[6]]	[values[0]]	0	1	1
[auto[1]]	[values[6]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[7]]	[values[4]]	0	1	1
[auto[1]]	[values[7]]	[values[6] , values[7]]	--	--	2

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	32	1			T285	32		-	-		-	-
auto[0]	values[0]	values[1]	2	1			T176	2		-	-		-	-
auto[0]	values[0]	values[2]	66	1			T220	22		T300	26		T104	12
auto[0]	values[0]	values[3]	24	1			T174	4		T238	6		T278	12
auto[0]	values[0]	values[4]	32	1			T249	16		T26	6		T188	10
auto[0]	values[0]	values[5]	54	1			T55	32		T170	20		T228	2
auto[0]	values[0]	values[6]	6	1			T243	6		-	-		-	-
auto[0]	values[0]	values[7]	36	1			T30	30		T301	6		-	-
auto[0]	values[1]	values[0]	22	1			T218	2		T191	4		T206	6
auto[0]	values[1]	values[2]	76	1			T79	20		T239	22		T302	14
auto[0]	values[1]	values[3]	2	1			T31	2		-	-		-	-
auto[0]	values[1]	values[4]	14	1			T29	14		-	-		-	-
auto[0]	values[1]	values[5]	30	1			T257	22		T171	8		-	-
auto[0]	values[1]	values[6]	114	1			T209	4		T303	12		T304	28
auto[0]	values[1]	values[7]	50	1			T185	2		T264	14		T248	10
auto[0]	values[2]	values[0]	4	1			T266	4		-	-		-	-
auto[0]	values[2]	values[1]	24	1			T195	20		T305	4		-	-
auto[0]	values[2]	values[2]	40	1			T216	4		T246	20		T306	4
auto[0]	values[2]	values[3]	24	1			T50	18		T307	6		-	-
auto[0]	values[2]	values[4]	84	1			T88	28		T308	14		T235	6
auto[0]	values[2]	values[5]	106	1			T1	36		T4	16		T254	28
auto[0]	values[2]	values[6]	60	1			T103	30		T309	24		T310	2
auto[0]	values[2]	values[7]	56	1			T8	8		T221	22		T251	6
auto[0]	values[3]	values[0]	24	1			T128	20		T311	4		-	-
auto[0]	values[3]	values[1]	30	1			T51	6		T101	14		T181	10
auto[0]	values[3]	values[2]	46	1			T168	6		T169	26		T269	2
auto[0]	values[3]	values[3]	24	1			T219	16		T196	2		T312	6
auto[0]	values[3]	values[4]	24	1			T46	6		T122	18		-	-
auto[0]	values[3]	values[5]	74	1			T94	2		T115	26		T199	14
auto[0]	values[3]	values[6]	40	1			T276	4		T313	36		-	-
auto[0]	values[4]	values[0]	10	1			T99	4		T223	2		T314	4
auto[0]	values[4]	values[1]	80	1			T59	26		T230	4		T204	16
auto[0]	values[4]	values[2]	8	1			T226	4		T275	4		-	-
auto[0]	values[4]	values[3]	92	1			T48	30		T236	20		T215	8
auto[0]	values[4]	values[4]	30	1			T173	20		T27	10		-	-
auto[0]	values[4]	values[5]	64	1			T194	26		T186	16		T198	22
auto[0]	values[4]	values[7]	90	1			T180	26		T232	4		T315	22
auto[0]	values[5]	values[0]	16	1			T211	2		T283	6		T316	4
auto[0]	values[5]	values[1]	18	1			T175	18		-	-		-	-
auto[0]	values[5]	values[2]	46	1			T129	8		T317	38		-	-
auto[0]	values[5]	values[3]	52	1			T177	12		T49	16		T182	10
auto[0]	values[5]	values[4]	48	1			T208	20		T279	28		-	-
auto[0]	values[5]	values[5]	10	1			T207	10		-	-		-	-
auto[0]	values[5]	values[6]	48	1			T67	30		T184	6		T258	12
auto[0]	values[5]	values[7]	34	1			T318	34		-	-		-	-
auto[0]	values[6]	values[0]	6	1			T319	2		T320	4		-	-
auto[0]	values[6]	values[1]	38	1			T214	32		T321	6		-	-
auto[0]	values[6]	values[2]	32	1			T25	10		T322	22		-	-
auto[0]	values[6]	values[3]	58	1			T9	4		T68	2		T102	8
auto[0]	values[6]	values[4]	10	1			T93	8		T323	2		-	-
auto[0]	values[6]	values[5]	58	1			T231	28		T284	26		T210	4
auto[0]	values[6]	values[6]	40	1			T244	12		T324	4		T325	24
auto[0]	values[6]	values[7]	18	1			T190	16		T326	2		-	-
auto[0]	values[7]	values[0]	32	1			T28	14		T97	18		-	-
auto[0]	values[7]	values[2]	32	1			T127	4		T252	4		T267	4
auto[0]	values[7]	values[3]	76	1			T45	26		T47	8		T259	6
auto[0]	values[7]	values[4]	50	1			T78	30		T200	20		-	-
auto[0]	values[7]	values[5]	38	1			T172	30		T327	8		-	-
auto[0]	values[7]	values[6]	8	1			T260	8		-	-		-	-
auto[0]	values[7]	values[7]	26	1			T263	14		T217	12		-	-
auto[1]	values[0]	values[0]	20	1			T86	20		-	-		-	-
auto[1]	values[0]	values[4]	2	1			T328	2		-	-		-	-
auto[1]	values[0]	values[5]	28	1			T282	28		-	-		-	-
auto[1]	values[0]	values[7]	24	1			T270	24		-	-		-	-
auto[1]	values[1]	values[4]	40	1			T83	14		T329	26		-	-
auto[1]	values[1]	values[5]	16	1			T250	8		T85	8		-	-
auto[1]	values[1]	values[6]	16	1			T255	16		-	-		-	-
auto[1]	values[2]	values[0]	16	1			T280	16		-	-		-	-
auto[1]	values[2]	values[1]	22	1			T77	8		T330	14		-	-
auto[1]	values[2]	values[2]	4	1			T193	4		-	-		-	-
auto[1]	values[2]	values[3]	22	1			T80	22		-	-		-	-
auto[1]	values[2]	values[5]	10	1			T240	2		T212	8		-	-
auto[1]	values[2]	values[6]	24	1			T331	24		-	-		-	-
auto[1]	values[3]	values[2]	24	1			T332	10		T253	14		-	-
auto[1]	values[3]	values[4]	32	1			T271	24		T333	8		-	-
auto[1]	values[3]	values[6]	18	1			T237	18		-	-		-	-
auto[1]	values[3]	values[7]	6	1			T57	6		-	-		-	-
auto[1]	values[4]	values[2]	10	1			T183	10		-	-		-	-
auto[1]	values[4]	values[3]	32	1			T273	22		T84	10		-	-
auto[1]	values[4]	values[4]	22	1			T281	22		-	-		-	-
auto[1]	values[4]	values[6]	40	1			T299	8		T75	32		-	-
auto[1]	values[5]	values[0]	12	1			T227	12		-	-		-	-
auto[1]	values[5]	values[5]	6	1			T178	6		-	-		-	-
auto[1]	values[5]	values[6]	14	1			T245	14		-	-		-	-
auto[1]	values[5]	values[7]	24	1			T82	24		-	-		-	-
auto[1]	values[6]	values[1]	58	1			T192	24		T87	34		-	-
auto[1]	values[6]	values[2]	38	1			T74	12		T334	26		-	-
auto[1]	values[6]	values[3]	12	1			T247	12		-	-		-	-
auto[1]	values[6]	values[4]	32	1			T66	14		T95	14		T179	4
auto[1]	values[6]	values[5]	18	1			T213	18		-	-		-	-
auto[1]	values[7]	values[0]	8	1			T242	8		-	-		-	-
auto[1]	values[7]	values[1]	36	1			T76	10		T335	26		-	-
auto[1]	values[7]	values[2]	32	1			T187	32		-	-		-	-
auto[1]	values[7]	values[3]	28	1			T81	28		-	-		-	-
auto[1]	values[7]	values[5]	64	1			T73	20		T96	38		T256	6