Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	66	0	66	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	64	0	64	100.00	100	1	1	64

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1599

1

T1

18

T4

8

T8

4

auto[1]

2101

1

T1

18

T4

8

T5

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	64	0	64	100.00

Automatically Generated Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	302	1			T5	5		T50	8		T66	4
auto[4:7]	300	1			T1	2		T4	2		T45	4
auto[8:11]	234	1			T1	2		T4	2		T5	3
auto[12:15]	4	1			T185	2		T197	2		-	-
auto[16:19]	20	1			T59	4		T173	2		T80	6
auto[20:23]	212	1			T1	6		T67	4		T55	2
auto[24:27]	30	1			T67	4		T172	4		T173	4
auto[28:31]	34	1			T73	6		T96	6		T78	6
auto[32:35]	12	1			T66	2		T213	2		T219	2
auto[36:39]	10	1			T300	4		T260	2		T280	4
auto[40:43]	22	1			T78	2		T271	6		T331	2
auto[44:47]	16	1			T45	2		T57	2		T213	4
auto[48:51]	10	1			T249	2		T78	2		T236	2
auto[52:55]	198	1			T4	2		T66	4		T45	2
auto[56:59]	288	1			T5	4		T9	4		T10	3
auto[60:63]	12	1			T80	4		T194	2		T336	4
auto[64:67]	10	1			T55	6		T285	4		-	-
auto[68:71]	24	1			T1	4		T28	2		T172	2
auto[72:75]	8	1			T173	2		T237	4		T330	2
auto[76:79]	8	1			T82	2		T239	2		T365	2
auto[80:83]	30	1			T30	6		T178	4		T271	2
auto[84:87]	14	1			T199	4		T331	2		T314	2
auto[88:91]	224	1			T45	10		T59	4		T79	2
auto[92:95]	6	1			T57	2		T239	2		T87	2
auto[96:99]	16	1			T1	4		T179	2		T273	4
auto[100:103]	8	1			T73	2		T225	2		T237	2
auto[104:107]	236	1			T1	2		T8	2		T70	6
auto[108:111]	6	1			T59	4		T366	2		-	-
auto[112:115]	12	1			T55	6		T75	2		T302	2
auto[116:119]	24	1			T30	4		T80	4		T249	2
auto[120:123]	22	1			T1	2		T221	2		T267	2
auto[124:127]	16	1			T190	6		T85	2		T239	4
auto[128:131]	18	1			T79	2		T80	2		T283	2
auto[132:135]	42	1			T29	2		T80	4		T180	4
auto[136:139]	22	1			T28	4		T259	2		T81	4
auto[140:143]	4	1			T242	2		T183	2		-	-
auto[144:147]	24	1			T30	2		T214	2		T83	4
auto[148:151]	16	1			T59	4		T75	2		T82	4
auto[152:155]	24	1			T67	2		T173	6		T221	2
auto[156:159]	144	1			T1	2		T67	4		T55	2
auto[160:163]	14	1			T73	4		T199	2		T83	2
auto[164:167]	12	1			T1	2		T204	2		T335	4
auto[168:171]	12	1			T95	4		T249	2		T187	2
auto[172:175]	10	1			T95	2		T299	2		T220	2
auto[176:179]	34	1			T4	6		T74	2		T194	6
auto[180:183]	92	1			T8	2		T67	2		T28	2
auto[184:187]	207	1			T10	5		T66	2		T67	2
auto[188:191]	14	1			T78	2		T279	8		T262	4
auto[192:195]	20	1			T88	4		T213	2		T199	2
auto[196:199]	14	1			T211	2		T73	2		T242	2
auto[200:203]	20	1			T59	2		T220	2		T215	2
auto[204:207]	18	1			T8	2		T96	4		T78	6
auto[208:211]	16	1			T59	2		T74	4		T302	2
auto[212:215]	22	1			T66	2		T194	4		T77	2
auto[216:219]	14	1			T245	8		T315	2		T285	4
auto[220:223]	18	1			T300	2		T85	2		T303	2
auto[224:227]	26	1			T245	2		T183	2		T284	6
auto[228:231]	24	1			T1	8		T55	2		T172	2
auto[232:235]	353	1			T1	2		T4	2		T5	6
auto[236:239]	22	1			T79	4		T273	2		T84	4
auto[240:243]	18	1			T79	2		T186	4		T225	2
auto[244:247]	26	1			T8	2		T29	2		T88	4
auto[248:251]	22	1			T55	4		T95	2		T307	2
auto[252:255]	10	1			T4	2		T177	2		T271	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	auto[0]	106	1			T50	4		T66	2		T67	3
auto[0:3]	auto[1]	196	1			T5	5		T50	4		T66	2
auto[4:7]	auto[0]	150	1			T1	1		T4	1		T45	2
auto[4:7]	auto[1]	150	1			T1	1		T4	1		T45	2
auto[8:11]	auto[0]	81	1			T1	1		T4	1		T68	1
auto[8:11]	auto[1]	153	1			T1	1		T4	1		T5	3
auto[12:15]	auto[0]	2	1			T185	1		T197	1		-	-
auto[12:15]	auto[1]	2	1			T185	1		T197	1		-	-
auto[16:19]	auto[0]	10	1			T59	2		T173	1		T80	3
auto[16:19]	auto[1]	10	1			T59	2		T173	1		T80	3
auto[20:23]	auto[0]	106	1			T1	3		T67	2		T55	1
auto[20:23]	auto[1]	106	1			T1	3		T67	2		T55	1
auto[24:27]	auto[0]	15	1			T67	2		T172	2		T173	2
auto[24:27]	auto[1]	15	1			T67	2		T172	2		T173	2
auto[28:31]	auto[0]	17	1			T73	3		T96	3		T78	3
auto[28:31]	auto[1]	17	1			T73	3		T96	3		T78	3
auto[32:35]	auto[0]	6	1			T66	1		T213	1		T219	1
auto[32:35]	auto[1]	6	1			T66	1		T213	1		T219	1
auto[36:39]	auto[0]	5	1			T300	2		T260	1		T280	2
auto[36:39]	auto[1]	5	1			T300	2		T260	1		T280	2
auto[40:43]	auto[0]	11	1			T78	1		T271	3		T331	1
auto[40:43]	auto[1]	11	1			T78	1		T271	3		T331	1
auto[44:47]	auto[0]	8	1			T45	1		T57	1		T213	2
auto[44:47]	auto[1]	8	1			T45	1		T57	1		T213	2
auto[48:51]	auto[0]	5	1			T249	1		T78	1		T236	1
auto[48:51]	auto[1]	5	1			T249	1		T78	1		T236	1
auto[52:55]	auto[0]	99	1			T4	1		T66	2		T45	1
auto[52:55]	auto[1]	99	1			T4	1		T66	2		T45	1
auto[56:59]	auto[0]	97	1			T9	2		T51	2		T55	2
auto[56:59]	auto[1]	191	1			T5	4		T9	2		T10	3
auto[60:63]	auto[0]	6	1			T80	2		T194	1		T336	2
auto[60:63]	auto[1]	6	1			T80	2		T194	1		T336	2
auto[64:67]	auto[0]	5	1			T55	3		T285	2		-	-
auto[64:67]	auto[1]	5	1			T55	3		T285	2		-	-
auto[68:71]	auto[0]	12	1			T1	2		T28	1		T172	1
auto[68:71]	auto[1]	12	1			T1	2		T28	1		T172	1
auto[72:75]	auto[0]	4	1			T173	1		T237	2		T330	1
auto[72:75]	auto[1]	4	1			T173	1		T237	2		T330	1
auto[76:79]	auto[0]	4	1			T82	1		T239	1		T365	1
auto[76:79]	auto[1]	4	1			T82	1		T239	1		T365	1
auto[80:83]	auto[0]	15	1			T30	3		T178	2		T271	1
auto[80:83]	auto[1]	15	1			T30	3		T178	2		T271	1
auto[84:87]	auto[0]	7	1			T199	2		T331	1		T314	1
auto[84:87]	auto[1]	7	1			T199	2		T331	1		T314	1
auto[88:91]	auto[0]	112	1			T45	5		T59	2		T79	1
auto[88:91]	auto[1]	112	1			T45	5		T59	2		T79	1
auto[92:95]	auto[0]	3	1			T57	1		T239	1		T87	1
auto[92:95]	auto[1]	3	1			T57	1		T239	1		T87	1
auto[96:99]	auto[0]	8	1			T1	2		T179	1		T273	2
auto[96:99]	auto[1]	8	1			T1	2		T179	1		T273	2
auto[100:103]	auto[0]	4	1			T73	1		T225	1		T237	1
auto[100:103]	auto[1]	4	1			T73	1		T225	1		T237	1
auto[104:107]	auto[0]	77	1			T1	1		T8	1		T79	1
auto[104:107]	auto[1]	159	1			T1	1		T8	1		T70	6
auto[108:111]	auto[0]	3	1			T59	2		T366	1		-	-
auto[108:111]	auto[1]	3	1			T59	2		T366	1		-	-
auto[112:115]	auto[0]	6	1			T55	3		T75	1		T302	1
auto[112:115]	auto[1]	6	1			T55	3		T75	1		T302	1
auto[116:119]	auto[0]	12	1			T30	2		T80	2		T249	1
auto[116:119]	auto[1]	12	1			T30	2		T80	2		T249	1
auto[120:123]	auto[0]	11	1			T1	1		T221	1		T267	1
auto[120:123]	auto[1]	11	1			T1	1		T221	1		T267	1
auto[124:127]	auto[0]	8	1			T190	3		T85	1		T239	2
auto[124:127]	auto[1]	8	1			T190	3		T85	1		T239	2
auto[128:131]	auto[0]	9	1			T79	1		T80	1		T283	1
auto[128:131]	auto[1]	9	1			T79	1		T80	1		T283	1
auto[132:135]	auto[0]	21	1			T29	1		T80	2		T180	2
auto[132:135]	auto[1]	21	1			T29	1		T80	2		T180	2
auto[136:139]	auto[0]	11	1			T28	2		T259	1		T81	2
auto[136:139]	auto[1]	11	1			T28	2		T259	1		T81	2
auto[140:143]	auto[0]	2	1			T242	1		T183	1		-	-
auto[140:143]	auto[1]	2	1			T242	1		T183	1		-	-
auto[144:147]	auto[0]	12	1			T30	1		T214	1		T83	2
auto[144:147]	auto[1]	12	1			T30	1		T214	1		T83	2
auto[148:151]	auto[0]	8	1			T59	2		T75	1		T82	2
auto[148:151]	auto[1]	8	1			T59	2		T75	1		T82	2
auto[152:155]	auto[0]	12	1			T67	1		T173	3		T221	1
auto[152:155]	auto[1]	12	1			T67	1		T173	3		T221	1
auto[156:159]	auto[0]	72	1			T1	1		T67	2		T55	1
auto[156:159]	auto[1]	72	1			T1	1		T67	2		T55	1
auto[160:163]	auto[0]	7	1			T73	2		T199	1		T83	1
auto[160:163]	auto[1]	7	1			T73	2		T199	1		T83	1
auto[164:167]	auto[0]	6	1			T1	1		T204	1		T335	2
auto[164:167]	auto[1]	6	1			T1	1		T204	1		T335	2
auto[168:171]	auto[0]	6	1			T95	2		T249	1		T187	1
auto[168:171]	auto[1]	6	1			T95	2		T249	1		T187	1
auto[172:175]	auto[0]	5	1			T95	1		T299	1		T220	1
auto[172:175]	auto[1]	5	1			T95	1		T299	1		T220	1
auto[176:179]	auto[0]	17	1			T4	3		T74	1		T194	3
auto[176:179]	auto[1]	17	1			T4	3		T74	1		T194	3
auto[180:183]	auto[0]	46	1			T8	1		T67	1		T28	1
auto[180:183]	auto[1]	46	1			T8	1		T67	1		T28	1
auto[184:187]	auto[0]	75	1			T66	1		T67	1		T128	2
auto[184:187]	auto[1]	132	1			T10	5		T66	1		T67	1
auto[188:191]	auto[0]	7	1			T78	1		T279	4		T262	2
auto[188:191]	auto[1]	7	1			T78	1		T279	4		T262	2
auto[192:195]	auto[0]	10	1			T88	2		T213	1		T199	1
auto[192:195]	auto[1]	10	1			T88	2		T213	1		T199	1
auto[196:199]	auto[0]	7	1			T211	1		T73	1		T242	1
auto[196:199]	auto[1]	7	1			T211	1		T73	1		T242	1
auto[200:203]	auto[0]	10	1			T59	1		T220	1		T215	1
auto[200:203]	auto[1]	10	1			T59	1		T220	1		T215	1
auto[204:207]	auto[0]	9	1			T8	1		T96	2		T78	3
auto[204:207]	auto[1]	9	1			T8	1		T96	2		T78	3
auto[208:211]	auto[0]	8	1			T59	1		T74	2		T302	1
auto[208:211]	auto[1]	8	1			T59	1		T74	2		T302	1
auto[212:215]	auto[0]	11	1			T66	1		T194	2		T77	1
auto[212:215]	auto[1]	11	1			T66	1		T194	2		T77	1
auto[216:219]	auto[0]	7	1			T245	4		T315	1		T285	2
auto[216:219]	auto[1]	7	1			T245	4		T315	1		T285	2
auto[220:223]	auto[0]	9	1			T300	1		T85	1		T303	1
auto[220:223]	auto[1]	9	1			T300	1		T85	1		T303	1
auto[224:227]	auto[0]	13	1			T245	1		T183	1		T284	3
auto[224:227]	auto[1]	13	1			T245	1		T183	1		T284	3
auto[228:231]	auto[0]	12	1			T1	4		T55	1		T172	1
auto[228:231]	auto[1]	12	1			T1	4		T55	1		T172	1
auto[232:235]	auto[0]	123	1			T1	1		T4	1		T50	5
auto[232:235]	auto[1]	230	1			T1	1		T4	1		T5	6
auto[236:239]	auto[0]	11	1			T79	2		T273	1		T84	2
auto[236:239]	auto[1]	11	1			T79	2		T273	1		T84	2
auto[240:243]	auto[0]	9	1			T79	1		T186	2		T225	1
auto[240:243]	auto[1]	9	1			T79	1		T186	2		T225	1
auto[244:247]	auto[0]	13	1			T8	1		T29	1		T88	2
auto[244:247]	auto[1]	13	1			T8	1		T29	1		T88	2
auto[248:251]	auto[0]	11	1			T55	2		T95	1		T307	1
auto[248:251]	auto[1]	11	1			T55	2		T95	1		T307	1
auto[252:255]	auto[0]	5	1			T4	1		T177	1		T271	1
auto[252:255]	auto[1]	5	1			T4	1		T177	1		T271	1