Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.26	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	2	58	96.67

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	2	58	96.67	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	116	1			T51	6		T127	2		T128	4
auto[ReadAddrCrossIntoMailbox]	40	1			T50	10		T128	2		T115	8
auto[ReadAddrCrossOutOfMailbox]	50	1			T128	4		T175	6		T115	10
auto[ReadAddrCrossAllMailbox]	40	1			T50	2		T127	2		T128	4
auto[ReadAddrOutsideMailbox]	696	1			T1	2		T4	4		T8	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

471

1

T1

1

T4

2

T8

1

auto[1]

471

1

T1

1

T4

2

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	176	1			T50	8		T66	4		T67	6
read_ops[0x0b]	146	1			T1	2		T4	2		T68	2
read_ops[0x3b]	178	1			T9	4		T51	4		T174	2
read_ops[0x6b]	138	1			T8	2		T79	2		T127	4
read_ops[0xbb]	134	1			T66	2		T67	2		T128	4
read_ops[0xeb]	170	1			T4	2		T50	10		T67	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	2	58	96.67	2

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x6b]]	[auto[ReadAddrCrossIntoMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T51	1		T122	4		T248	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T51	1		T122	4		T248	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	6	1			T50	3		T195	1		T308	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	6	1			T50	3		T195	1		T308	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T308	2		T243	1		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T308	2		T243	1		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T195	1		T308	1		T248	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	5	1			T195	1		T308	1		T248	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	66	1			T50	1		T66	2		T67	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	66	1			T50	1		T66	2		T67	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	11	1			T128	1		T48	1		T257	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	11	1			T128	1		T48	1		T257	3
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T115	3		T308	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T115	3		T308	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	4	1			T128	1		T175	1		T115	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T128	1		T175	1		T115	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T175	1		T308	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T175	1		T308	1		-	-
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	52	1			T1	1		T4	1		T68	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	52	1			T1	1		T4	1		T68	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	15	1			T51	2		T48	3		T263	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	15	1			T51	2		T48	3		T263	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T129	1		T353	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T129	1		T353	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T115	1		T97	1		T129	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T115	1		T97	1		T129	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T115	1		T195	1		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T115	1		T195	1		-	-
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	65	1			T9	2		T174	1		T46	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	65	1			T9	2		T174	1		T46	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T127	1		T175	1		T257	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T127	1		T175	1		T257	3
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T175	1		T195	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T175	1		T195	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T127	1		T128	1		T175	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T127	1		T128	1		T175	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	57	1			T8	1		T79	1		T128	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	57	1			T8	1		T79	1		T128	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T175	1		T207	3		T233	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T175	1		T207	3		T233	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T128	1		T129	1		T354	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T128	1		T129	1		T354	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	8	1			T128	1		T175	1		T115	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	8	1			T128	1		T175	1		T115	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T175	2		T115	1		T327	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T175	2		T115	1		T327	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	44	1			T66	1		T67	1		T177	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	44	1			T66	1		T67	1		T177	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	11	1			T128	1		T48	1		T263	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	11	1			T128	1		T48	1		T263	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T50	2		T115	1		T195	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T50	2		T115	1		T195	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T115	1		T263	2		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T115	1		T263	2		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T50	1		T128	1		T327	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T50	1		T128	1		T327	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	64	1			T4	1		T50	2		T67	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	64	1			T4	1		T50	2		T67	3