Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	211919	1			T1	1		T2	21		T4	1
all_pins[1]	211919	1			T1	1		T2	21		T4	1
all_pins[2]	211919	1			T1	1		T2	21		T4	1
all_pins[3]	211919	1			T1	1		T2	21		T4	1
all_pins[4]	211919	1			T1	1		T2	21		T4	1
all_pins[5]	211919	1			T1	1		T2	21		T4	1
all_pins[6]	211919	1			T1	1		T2	21		T4	1
all_pins[7]	211919	1			T1	1		T2	21		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1694415	1			T1	8		T2	143		T4	8
values[0x1]	937	1			T2	25		T42	46		T43	58
transitions[0x0=>0x1]	683	1			T2	18		T42	34		T43	39
transitions[0x1=>0x0]	696	1			T2	18		T42	34		T43	39

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	211781	1			T1	1		T2	19		T4	1
all_pins[0]	values[0x1]	138	1			T2	2		T42	4		T43	8
all_pins[0]	transitions[0x0=>0x1]	101	1			T2	1		T42	4		T43	6
all_pins[0]	transitions[0x1=>0x0]	83	1			T2	2		T42	6		T43	1
all_pins[1]	values[0x0]	211799	1			T1	1		T2	18		T4	1
all_pins[1]	values[0x1]	120	1			T2	3		T42	6		T43	3
all_pins[1]	transitions[0x0=>0x1]	83	1			T2	2		T42	3		T163	6
all_pins[1]	transitions[0x1=>0x0]	70	1			T2	5		T42	4		T43	7
all_pins[2]	values[0x0]	211812	1			T1	1		T2	15		T4	1
all_pins[2]	values[0x1]	107	1			T2	6		T42	7		T43	10
all_pins[2]	transitions[0x0=>0x1]	83	1			T2	4		T42	4		T43	9
all_pins[2]	transitions[0x1=>0x0]	74	1			T2	2		T42	4		T43	5
all_pins[3]	values[0x0]	211821	1			T1	1		T2	17		T4	1
all_pins[3]	values[0x1]	98	1			T2	4		T42	7		T43	6
all_pins[3]	transitions[0x0=>0x1]	72	1			T2	2		T42	6		T43	5
all_pins[3]	transitions[0x1=>0x0]	90	1			T2	1		T42	4		T43	7
all_pins[4]	values[0x0]	211803	1			T1	1		T2	18		T4	1
all_pins[4]	values[0x1]	116	1			T2	3		T42	5		T43	8
all_pins[4]	transitions[0x0=>0x1]	104	1			T2	3		T42	4		T43	5
all_pins[4]	transitions[0x1=>0x0]	70	1			T2	2		T42	5		T43	3
all_pins[5]	values[0x0]	211837	1			T1	1		T2	19		T4	1
all_pins[5]	values[0x1]	82	1			T2	2		T42	6		T43	6
all_pins[5]	transitions[0x0=>0x1]	61	1			T2	2		T42	5		T43	3
all_pins[5]	transitions[0x1=>0x0]	120	1			T2	4		T42	4		T43	10
all_pins[6]	values[0x0]	211778	1			T1	1		T2	17		T4	1
all_pins[6]	values[0x1]	141	1			T2	4		T42	5		T43	13
all_pins[6]	transitions[0x0=>0x1]	96	1			T2	4		T42	3		T43	10
all_pins[6]	transitions[0x1=>0x0]	90	1			T2	1		T42	4		T43	1
all_pins[7]	values[0x0]	211784	1			T1	1		T2	20		T4	1
all_pins[7]	values[0x1]	135	1			T2	1		T42	6		T43	4
all_pins[7]	transitions[0x0=>0x1]	83	1			T42	5		T43	1		T163	5
all_pins[7]	transitions[0x1=>0x0]	99	1			T2	1		T42	3		T43	5