Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.07	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	51	77	60.16

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	51	77	60.16	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	388	1			T68	2		T172	30		T30	30
values[1]	372	1			T4	16		T50	18		T128	20
values[2]	372	1			T8	8		T9	4		T67	30
values[3]	544	1			T66	14		T173	20		T47	8
values[4]	370	1			T1	36		T51	6		T59	26
values[5]	480	1			T55	32		T79	20		T127	4
values[6]	254	1			T45	26		T57	6		T174	4
values[7]	418	1			T175	18		T176	2		T75	32

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	504	1			T66	14		T67	30		T51	6
values[1]	294	1			T9	4		T50	18		T174	4
values[2]	372	1			T1	36		T4	16		T57	6
values[3]	348	1			T68	2		T29	14		T94	2
values[4]	528	1			T79	20		T172	30		T177	12
values[5]	312	1			T8	8		T59	26		T127	4
values[6]	292	1			T175	18		T96	38		T178	6
values[7]	548	1			T45	26		T46	6		T176	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3148

1

T1

36

T4

16

T8

8

auto[1]

50

1

T73

2

T75

4

T76

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	51	77	60.16	51

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[6]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[6]]	[values[3]]	0	1	1
[auto[1]]	[values[0]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[0]]	[values[3]]	0	1	1
[auto[1]]	[values[0]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[1]]	[values[1]]	0	1	1
[auto[1]]	[values[1]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5
[auto[1]]	[values[2]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[2]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[3]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[3]]	[values[4]]	0	1	1
[auto[1]]	[values[3]]	[values[7]]	0	1	1
[auto[1]]	[values[4]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[4]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[5]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[5]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[5]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[7]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[7]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[7]]	[values[7]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	40	1			T179	4		T180	26		T181	10
auto[0]	values[0]	values[1]	28	1			T182	10		T183	10		T184	6
auto[0]	values[0]	values[2]	44	1			T185	2		T186	16		T187	26
auto[0]	values[0]	values[3]	26	1			T68	2		T123	24		-	-
auto[0]	values[0]	values[4]	134	1			T172	30		T73	18		T102	8
auto[0]	values[0]	values[5]	30	1			T30	30		-	-		-	-
auto[0]	values[0]	values[6]	34	1			T188	10		T189	24		-	-
auto[0]	values[0]	values[7]	44	1			T190	16		T191	4		T192	24
auto[0]	values[1]	values[0]	70	1			T128	20		T169	26		T82	22
auto[0]	values[1]	values[1]	78	1			T50	18		T193	4		T88	28
auto[0]	values[1]	values[2]	50	1			T4	16		T74	12		T85	6
auto[0]	values[1]	values[3]	48	1			T94	2		T194	26		T26	6
auto[0]	values[1]	values[4]	42	1			T195	20		T196	2		T197	20
auto[0]	values[1]	values[5]	22	1			T198	22		-	-		-	-
auto[0]	values[1]	values[6]	14	1			T199	14		-	-		-	-
auto[0]	values[1]	values[7]	44	1			T200	20		T201	8		T202	16
auto[0]	values[2]	values[0]	108	1			T67	30		T49	16		T203	2
auto[0]	values[2]	values[1]	32	1			T9	4		T204	16		T205	2
auto[0]	values[2]	values[2]	6	1			T206	6		-	-		-	-
auto[0]	values[2]	values[3]	34	1			T207	10		T208	20		T209	4
auto[0]	values[2]	values[4]	42	1			T115	26		T83	12		T210	4
auto[0]	values[2]	values[5]	20	1			T8	8		T211	2		T212	8
auto[0]	values[2]	values[6]	18	1			T213	18		-	-		-	-
auto[0]	values[2]	values[7]	110	1			T168	6		T214	32		T215	8
auto[0]	values[3]	values[0]	148	1			T66	14		T173	20		T76	8
auto[0]	values[3]	values[1]	36	1			T216	4		T101	14		T99	4
auto[0]	values[3]	values[2]	116	1			T80	22		T170	20		T217	12
auto[0]	values[3]	values[3]	72	1			T218	2		T219	16		T220	22
auto[0]	values[3]	values[4]	26	1			T221	22		T100	4		-	-
auto[0]	values[3]	values[5]	52	1			T222	18		T223	2		T224	20
auto[0]	values[3]	values[6]	32	1			T225	20		T226	4		T227	8
auto[0]	values[3]	values[7]	46	1			T47	8		T77	8		T228	2
auto[0]	values[4]	values[0]	10	1			T51	6		T229	4		-	-
auto[0]	values[4]	values[1]	12	1			T129	8		T230	4		-	-
auto[0]	values[4]	values[2]	76	1			T1	36		T231	28		T232	4
auto[0]	values[4]	values[3]	16	1			T233	16		-	-		-	-
auto[0]	values[4]	values[4]	66	1			T177	12		T234	22		T235	6
auto[0]	values[4]	values[5]	72	1			T59	26		T236	20		T237	18
auto[0]	values[4]	values[6]	70	1			T96	38		T238	6		T239	22
auto[0]	values[4]	values[7]	46	1			T46	6		T240	2		T241	2
auto[0]	values[5]	values[0]	58	1			T55	32		T95	14		T242	8
auto[0]	values[5]	values[1]	36	1			T78	30		T243	6		-	-
auto[0]	values[5]	values[2]	34	1			T28	14		T81	20		-	-
auto[0]	values[5]	values[3]	50	1			T29	14		T244	12		T245	14
auto[0]	values[5]	values[4]	102	1			T79	20		T246	20		T247	12
auto[0]	values[5]	values[5]	72	1			T127	4		T248	10		T84	8
auto[0]	values[5]	values[6]	34	1			T178	6		T122	18		T27	10
auto[0]	values[5]	values[7]	84	1			T249	16		T250	8		T251	6
auto[0]	values[6]	values[0]	4	1			T252	4		-	-		-	-
auto[0]	values[6]	values[1]	50	1			T174	4		T253	14		T254	28
auto[0]	values[6]	values[2]	28	1			T57	6		T255	16		T256	6
auto[0]	values[6]	values[4]	34	1			T257	22		T258	12		-	-
auto[0]	values[6]	values[5]	14	1			T259	6		T260	8		-	-
auto[0]	values[6]	values[6]	28	1			T261	6		T262	22		-	-
auto[0]	values[6]	values[7]	96	1			T45	26		T48	30		T25	10
auto[0]	values[7]	values[0]	60	1			T263	14		T264	14		T265	4
auto[0]	values[7]	values[1]	22	1			T266	4		T267	4		T268	6
auto[0]	values[7]	values[2]	2	1			T269	2		-	-		-	-
auto[0]	values[7]	values[3]	94	1			T75	28		T103	30		T270	24
auto[0]	values[7]	values[4]	76	1			T271	24		T272	2		T273	22
auto[0]	values[7]	values[5]	24	1			T274	20		T275	4		-	-
auto[0]	values[7]	values[6]	54	1			T175	18		T276	4		T277	8
auto[0]	values[7]	values[7]	78	1			T176	2		T278	12		T279	28
auto[1]	values[0]	values[2]	6	1			T187	6		-	-		-	-
auto[1]	values[0]	values[4]	2	1			T73	2		-	-		-	-
auto[1]	values[1]	values[0]	2	1			T82	2		-	-		-	-
auto[1]	values[1]	values[2]	2	1			T85	2		-	-		-	-
auto[1]	values[2]	values[4]	2	1			T83	2		-	-		-	-
auto[1]	values[3]	values[0]	4	1			T76	2		T87	2		-	-
auto[1]	values[3]	values[3]	4	1			T86	4		-	-		-	-
auto[1]	values[3]	values[5]	4	1			T280	4		-	-		-	-
auto[1]	values[3]	values[6]	4	1			T227	4		-	-		-	-
auto[1]	values[4]	values[4]	2	1			T281	2		-	-		-	-
auto[1]	values[5]	values[2]	8	1			T81	8		-	-		-	-
auto[1]	values[5]	values[5]	2	1			T84	2		-	-		-	-
auto[1]	values[7]	values[3]	4	1			T75	4		-	-		-	-
auto[1]	values[7]	values[6]	4	1			T282	4		-	-		-	-